Datasheet

PIC16(L)F1824/8
DS40001419F-page 278  2010-2015 Microchip Technology Inc.
25.7 Baud Rate Generator
The MSSP1 module has a Baud Rate Generator avail-
able for clock generation in both I
2
C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSP1ADD register (Register 25-6).
When a write occurs to SSP1BUF, the Baud Rate
Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 25-40 triggers the
value from SSP1ADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP1 is
being operated in.
Table 25-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSP1ADD.
EQUATION 25-1:
FIGURE 25-40: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 25-4: MSSP1 CLOCK RATE W/BRG
FCLOCK
FOSC
SSPxADD 1+4
-------------------------------------------------=
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSP1ADD when used as a Baud Rate
Generator for I
2
C. This is an implementation
limitation.
F
OSC FCY BRG Value
F
CLOCK
(2 Rollovers of BRG)
32 MHz 8 MHz 13h 400 kHz
32 MHz 8 MHz 19h 308 kHz
32 MHz 8 MHz 4Fh 100 kHz
16 MHz 4 MHz 09h 400 kHz
16 MHz 4 MHz 0Ch 308 kHz
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 09h 100 kHz
Note: Refer to the I/O port electrical and timing specifications in Table 30-4 and Figure 30-7 to ensure the system
is designed to support the I/O requirements.
SSP1M<3:0>
BRG Down Counter
SSP1CLK
F
OSC/2
SSP1ADD<7:0>
SSP1M<3:0>
SCL
Reload
Control
Reload