Datasheet

PIC16(L)F1824/8
DS40001419F-page 204  2010-2015 Microchip Technology Inc.
24.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (F
OSC/4), or by an external clock source.
When Timer1 is clocked by F
OSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
24.1.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default loca-
tions are upon a Reset, see Section 12.1 “Alternate
Pin Function” for more information.
TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON1
— — — — P1DSEL P1CSEL P2BSEL CCP2SEL 118
CCPxCON PxM<1:0>
(1)
DCxB<1:0> CCPxM<3:0>
225
CCPRxL Capture/Compare/PWM Register x Low Byte (LSB)
203*
CCPRxH Capture/Compare/PWM Register x High Byte (MSB)
203*
CMxCON0 CxON CxOUT CxOE CxPOL
— CxSP CxHYS CxSYNC
171
CMxCON1 CxINTP CxINTN CxPCH<1:0>
— — CxNCH<1:0>
172
INLVLA
— —INLVLA5INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 123
INLVLC
INLVLC7
(2)
INLVLC6
(2)
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 134
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
89
PIE1 TMR1GIE
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
90
PIE2
OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE
91
PIE3
—
—
CCP4IE CCP3IE TMR6IE
—TMR4IE—
92
PIR1 TMR1GIF
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
93
PIR2
OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF
94
PIR3
—
—
CCP4IF CCP3IF TMR6IF
—TMR4IF—
95
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—TMR1ON
186
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS1 T1GSS0
187
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
182*
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
182*
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
121
TRISC
TRISC7
(2)
TRISC6
(2)
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
132
Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by the Capture.
* Page provides register information.
Note 1: Applies to ECCP modules only.
2: PIC16(L)F1828 only.