Datasheet
Table Of Contents
- High-Performance RISC CPU
- Flexible Oscillator Structure
- Special Microcontroller Features
- Extreme Low-Power Management PIC12LF1822/16LF1823 with XLP
- Analog Features
- Peripheral Highlights
- Peripheral Features (Continued)
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 2.0 Enhanced Mid-Range CPU
- 3.0 Memory Organization
- 3.1 Program Memory Organization
- 3.2 Data Memory Organization
- 3.2.1 Core Registers
- 3.2.2 Special Function Register
- 3.2.3 General Purpose RAM
- 3.2.4 Common RAM
- 3.2.5 Device Memory Maps
- TABLE 3-2: Memory Map Tables
- TABLE 3-3: PIC12(L)F1822/16(L)F1823 Memory Map, Banks 0-7
- TABLE 3-4: PIC12(L)F1822/16(L)F1823 Memory Map, Banks 8-15
- TABLE 3-5: PIC12(L)F1822/16(L)F1823 Memory Map, Banks 16-23
- TABLE 3-6: PIC12(L)F1822/16(L)F1823 Memory Map, Banks 24-31
- TABLE 3-7: PIC12(L)F1822/16(L)F1823 Memory Map, Bank 31
- 3.2.6 Special Function Registers Summary
- 3.3 PCL and PCLATH
- 3.4 Stack
- 3.5 Indirect Addressing
- 4.0 Device Configuration
- 5.0 Oscillator Module (With Fail-Safe Clock Monitor)
- 6.0 Reference Clock Module
- 7.0 Resets
- FIGURE 7-1: Simplified Block Diagram Of On-Chip Reset Circuit
- 7.1 Power-on Reset (POR)
- 7.2 Brown-Out Reset (BOR)
- 7.3 MCLR
- 7.4 Watchdog Timer (WDT) Reset
- 7.5 RESET Instruction
- 7.6 Stack Overflow/Underflow Reset
- 7.7 Programming Mode Exit
- 7.8 Power-Up Timer
- 7.9 Start-up Sequence
- 7.10 Determining the Cause of a Reset
- 7.11 Power Control (PCON) Register
- 8.0 Interrupts
- 9.0 Power-Down Mode (Sleep)
- 10.0 Watchdog Timer
- 11.0 Data EEPROM and Flash Program Memory Control
- 11.1 EEADRL and EEADRH Registers
- 11.2 Using the Data EEPROM
- 11.3 Flash Program Memory Overview
- 11.4 Modifying Flash Program Memory
- 11.5 User ID, Device ID and Configuration Word Access
- 11.6 Write Verify
- EXAMPLE 11-6: EEPROM Write Verify
- Register 11-1: EEDATL: EEPROM Data Register
- Register 11-2: EEDATH: EEPROM Data High Byte Register
- Register 11-3: EEADRL: EEPROM Address Register
- Register 11-4: EEADRH: EEPROM Address High Byte Register
- Register 11-5: EECON1: EEPROM Control 1 Register
- Register 11-6: EECON2: EEPROM Control 2 Register
- TABLE 11-3: Summary of Registers Associated with Data EEPROM
- 12.0 I/O Ports
- TABLE 12-1: Port Availability Per Device
- FIGURE 12-1: Generic I/O Port Operation
- 12.1 Alternate Pin Function
- 12.2 PORTA Registers
- 12.2.1 ANSELA Register
- 12.2.2 PORTA Functions and Output Priorities
- Register 12-2: PORTA: PORTA Register
- Register 12-3: TRISA: PORTA Tri-State Register
- Register 12-4: LATA: PORTA Data Latch Register
- Register 12-5: ANSELA: PORTA Analog Select Register
- Register 12-6: WPUA: Weak Pull-up PORTA Register
- TABLE 12-2: Summary of Registers Associated with PORTA
- TABLE 12-3: Summary of Configuration Word with PORTA
- 12.3 PORTC Registers (PIC16(L)F1823 only)
- 13.0 Interrupt-On-Change
- 13.1 Enabling the Module
- 13.2 Individual Pin Configuration
- 13.3 Interrupt Flags
- 13.4 Clearing Interrupt Flags
- 13.5 Operation in Sleep
- FIGURE 13-1: Interrupt-On-Change Block Diagram
- Register 13-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register
- Register 13-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register
- Register 13-3: IOCAF: Interrupt-on-Change PORTA Flag Register
- TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change
- 14.0 Fixed Voltage Reference (FVR)
- 15.0 Temperature Indicator Module
- 16.0 Analog-to-Digital Converter (ADC) Module
- FIGURE 16-1: ADC Block Diagram
- 16.1 ADC Configuration
- 16.2 ADC Operation
- 16.2.1 Starting a Conversion
- 16.2.2 Completion of a Conversion
- 16.2.3 Terminating a Conversion
- 16.2.4 ADC Operation During Sleep
- 16.2.5 Special Event Trigger
- 16.2.6 A/D Conversion Procedure
- 16.2.7 ADC Register Definitions
- Register 16-1: ADCON0: A/D Control Register 0
- Register 16-2: ADCON1: A/D Control Register 1
- Register 16-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0
- Register 16-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0
- Register 16-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1
- Register 16-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1
- 16.3 A/D Acquisition Requirements
- 17.0 Digital-to-Analog Converter (DAC) Module
- 18.0 SR Latch
- 19.0 Comparator Module
- 19.1 Comparator Overview
- 19.2 Comparator Control
- 19.3 Comparator Hysteresis
- 19.4 Timer1 Gate Operation
- 19.5 Comparator Interrupt
- 19.6 Comparator Positive Input Selection
- 19.7 Comparator Negative Input Selection
- 19.8 Comparator Response Time
- 19.9 Interaction with ECCP Logic
- 19.10 Analog Input Connection Considerations
- 20.0 Timer0 Module
- 21.0 Timer1 Module with Gate Control
- FIGURE 21-1: Timer1 Block Diagram
- 21.1 Timer1 Operation
- 21.2 Clock Source Selection
- 21.3 Timer1 Prescaler
- 21.4 Timer1 Oscillator
- 21.5 Timer1 Operation in Asynchronous Counter Mode
- 21.6 Timer1 Gate
- 21.7 Timer1 Interrupt
- 21.8 Timer1 Operation During Sleep
- 21.9 ECCP/CCP Capture/Compare Time Base
- 21.10 ECCP/CCP Special Event Trigger
- 21.11 Timer1 Control Register
- 21.12 Timer1 Gate Control Register
- 22.0 Timer2 Module
- 23.0 Data Signal Modulator
- FIGURE 23-1: Simplified Block Diagram of the Data Signal Modulator
- 23.1 DSM Operation
- 23.2 Modulator Signal Sources
- 23.3 Carrier Signal Sources
- 23.4 Carrier Synchronization
- FIGURE 23-2: On OFF Keying (OOK) Synchronization
- EXAMPLE 23-1: No Synchronization (MDSHSYNC = 0, MDCLSYNC = 0)
- FIGURE 23-3: Carrier High Synchronization (MDSHSYNC = 1, MDCLSYNC = 0)
- FIGURE 23-4: Carrier Low Synchronization (MDSHSYNC = 0, MDCLSYNC = 1)
- FIGURE 23-5: Full Synchronization (MDSHSYNC = 1, MDCLSYNC = 1)
- 23.5 Carrier Source Polarity Select
- 23.6 Carrier Source Pin Disable
- 23.7 Programmable Modulator Data
- 23.8 Modulator Source Pin Disable
- 23.9 Modulated Output Polarity
- 23.10 Slew Rate Control
- 23.11 Operation in Sleep Mode
- 23.12 Effects of a Reset
- Register 23-1: MDCON: Modulation Control Register
- Register 23-2: MDSRC: Modulation Source Control Register
- Register 23-3: MDCARH: Modulation High Carrier Control Register
- Register 23-4: MDCARL: Modulation Low Carrier Control Register
- TABLE 23-1: Summary of Registers Associated with Data Signal Modulator Mode
- 24.0 Capture/Compare/PWM Modules
- TABLE 24-1: PWM Resources
- 24.1 Capture Mode
- 24.2 Compare Mode
- 24.3 PWM Overview
- 24.4 PWM (Enhanced Mode)
- FIGURE 24-5: Example Simplified Block Diagram of the Enhanced PWM Mode
- TABLE 24-9: Example Pin Assignments for Various PWM Enhanced Modes
- FIGURE 24-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)
- FIGURE 24-7: Example Enhanced PWM Output Relationships (Active-Low State)
- 24.4.1 Half-Bridge Mode
- 24.4.2 Full-Bridge Mode (PIC16(L)F1823 only)
- 24.4.3 Enhanced PWM Auto- shutdown mode
- 24.4.4 Auto-Restart Mode
- 24.4.5 Programmable Dead-Band Delay Mode
- 24.4.6 PWM Steering Mode
- 24.4.7 Start-up Considerations
- 24.4.8 Alternate Pin Locations
- 25.0 Master Synchronous Serial Port Module
- 25.1 Master SSP (MSSP1) Module Overview
- 25.2 SPI Mode Overview
- 25.3 I2C Mode Overview
- 25.4 I2C Mode Operation
- 25.5 I2C Slave Mode Operation
- 25.5.1 Slave Mode Addresses
- 25.5.2 Slave Reception
- FIGURE 25-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)
- FIGURE 25-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)
- FIGURE 25-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)
- FIGURE 25-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)
- 25.5.3 SLAVE Transmission
- 25.5.4 Slave mode 10-bit Address Reception
- 25.5.5 10-bit Addressing With Address Or Data Hold
- 25.5.6 Clock Stretching
- 25.5.7 Clock Synchronization and the CKP bit
- 25.5.8 General Call Address Support
- 25.5.9 SSP1 Mask Register
- 25.6 I2C Master Mode
- 25.6.1 I2C Master Mode Operation
- 25.6.2 Clock Arbitration
- 25.6.3 WCOL Status Flag
- 25.6.4 I2C Master Mode Start Condition Timing
- 25.6.5 I2C Master Mode Repeated Start Condition Timing
- 25.6.6 I2C Master Mode Transmission
- 25.6.7 I2C Master Mode Reception
- 25.6.8 Acknowledge Sequence Timing
- 25.6.9 Stop Condition Timing
- 25.6.10 Sleep Operation
- 25.6.11 Effects of a Reset
- 25.6.12 Multi-Master Mode
- 25.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration
- FIGURE 25-32: Bus Collision Timing for Transmit and Acknowledge
- FIGURE 25-33: Bus Collision During Start Condition (SDA Only)
- FIGURE 25-34: Bus Collision During Start Condition (SCL = 0)
- FIGURE 25-35: BRG Reset Due to Sda Arbitration During Start Condition
- FIGURE 25-36: Bus Collision During a Repeated Start Condition (Case 1)
- FIGURE 25-37: Bus Collision During Repeated Start Condition (Case 2)
- FIGURE 25-38: Bus Collision During a Stop Condition (Case 1)
- FIGURE 25-39: Bus Collision During a Stop Condition (Case 2)
- TABLE 25-3: Summary of Registers Associated with I2C™ Operation
- 25.7 Baud Rate Generator
- FIGURE 25-40: Baud Rate Generator Block Diagram
- TABLE 25-4: MSSP1 Clock Rate w/BRG
- Register 25-1: SSP1STAT: SSP1 STATUS Register
- Register 25-2: SSP1CON1: SSP1 Control Register 1
- Register 25-3: SSP1CON2: SSP1 Control Register 2
- Register 25-4: SSP1CON3: SSP1 Control Register 3
- Register 25-5: SSP1MSK: SSP1 Mask Register
- Register 25-6: SSP1ADD: MSSP1 Address and Baud Rate Register (I2C Mode)
- 26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- FIGURE 26-1: EUSART Transmit Block Diagram
- FIGURE 26-2: EUSART Receive Block Diagram
- 26.1 EUSART Asynchronous Mode
- 26.2 Clock Accuracy with Asynchronous Operation
- 26.3 EUSART Baud Rate Generator (BRG)
- EXAMPLE 26-1: Calculating Baud Rate Error
- TABLE 26-3: Baud Rate Formulas
- TABLE 26-4: Summary of Registers associated with the Baud Rate Generator
- TABLE 26-5: Baud Rates for Asynchronous Modes
- 26.3.1 Auto-Baud Detect
- 26.3.2 Auto-baud Overflow
- 26.3.3 Auto-Wake-up on Break
- 26.3.4 BREAK Character Sequence
- 26.3.5 Receiving a BREAK Character
- 26.4 EUSART Synchronous Mode
- 26.4.1 Synchronous Master Mode
- FIGURE 26-10: Synchronous Transmission
- FIGURE 26-11: Synchronous Transmission (Through TXEN)
- TABLE 26-7: Summary of Registers Associated with Synchronous Master Transmission
- FIGURE 26-12: Synchronous Reception (Master Mode, SREN)
- TABLE 26-8: Summary of Registers Associated with Synchronous Master Reception
- 26.4.2 Synchronous Slave Mode
- 26.4.1 Synchronous Master Mode
- 26.5 EUSART Operation During Sleep
- 27.0 Capacitive Sensing (CPS) Module
- 28.0 In-Circuit Serial Programming™ (ICSP™)
- 29.0 Instruction Set Summary
- 30.0 Electrical Specifications
- Absolute Maximum Ratings(†)
- 30.1 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended)
- 30.2 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended)
- 30.3 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Power-Down)
- 30.4 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E
- 30.5 Memory Programming Requirements
- 30.6 Thermal Considerations
- 30.7 Timing Parameter Symbology
- 30.8 AC Characteristics: PIC12(L)F1822/16(L)F1823-I/E
- FIGURE 30-6: Clock Timing
- TABLE 30-1: Clock Oscillator Timing Requirements
- TABLE 30-2: Oscillator Parameters
- TABLE 30-3: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V)
- FIGURE 30-7: CLKOUT and I/O Timing
- TABLE 30-4: CLKOUT and I/O Timing Parameters
- FIGURE 30-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- FIGURE 30-9: Brown-Out Reset Timing and Characteristics
- TABLE 30-5: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters
- FIGURE 30-10: Timer0 and Timer1 External Clock Timings
- TABLE 30-6: Timer0 and Timer1 External Clock Requirements
- FIGURE 30-11: Capture/Compare/PWM Timings (CCP)
- TABLE 30-7: Capture/Compare/PWM Requirements (CCP)
- TABLE 30-8: Analog-to-Digital Converter (ADC) Characteristics:(1, 2, 3)
- TABLE 30-9: ADC Conversion Requirements
- FIGURE 30-12: PIC12(L)F1822/16(L)F1823 A/D Conversion Timing (Normal Mode)
- FIGURE 30-13: PIC12(L)F1822/16(L)F1823 A/D Conversion Timing (Sleep Mode)
- TABLE 30-10: Comparator Specifications
- TABLE 30-11: Digital-to-Analog Converter (DAC) Specifications
- FIGURE 30-14: USART Synchronous Transmission (Master/Slave) Timing
- TABLE 30-12: USART Synchronous Transmission Requirements
- FIGURE 30-15: USART Synchronous Receive (Master/Slave) Timing
- TABLE 30-13: USART Synchronous Receive Requirements
- FIGURE 30-16: SPI Master Mode Timing (CKE = 0, SMP = 0)
- FIGURE 30-17: SPI Master Mode Timing (CKE = 1, SMP = 1)
- FIGURE 30-18: SPI Slave Mode Timing (CKE = 0)
- FIGURE 30-19: SPI Slave Mode Timing (CKE = 1)
- TABLE 30-14: SPI Mode Requirements
- FIGURE 30-20: I2C™ Bus Start/Stop Bits Timing
- FIGURE 30-21: I2C™ Bus Data Timing
- TABLE 30-15: I2C™ Bus Start/Stop Bits Requirements
- TABLE 30-16: I2C™ Bus Data Requirements
- TABLE 30-17: Cap Sense Oscillator Specifications
- FIGURE 30-22: Cap Sense Oscillator
- 30.9 High Temperature Operation
- TABLE 30-18: Absolute Maximum Ratings
- FIGURE 30-23: PIC12F1822/16F1823 Voltage Frequency Graph, -40°C £ Ta £ +150°C
- FIGURE 30-24: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature
- TABLE 30-19: DC Characteristics for PIC12F1822/16F1823-H (High Temp.)
- TABLE 30-20: Memory Programming Requirements for PIC12F1822/16F1823-H (High Temp.)
- TABLE 30-21: Oscillator Parameters for PIC12F1822/16F1823-H (High Temp.)
- TABLE 30-22: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters for PIC12F1822/16F1823-H (High Temp.)
- TABLE 30-23: A/D Converter (ADC) Characteristics for PIC12F1822/16F1823-H (High Temp.)
- TABLE 30-24: Comparator Specifications for PIC12F1822/16F1823-H (High Temp.)
- TABLE 30-25: Cap Sense Oscillator Specifications for PIC12F1822/16F1823-H (High Temp.)
- 31.0 DC and AC Characteristics Graphs and Charts
- FIGURE 31-1: Idd, LP Oscillator Mode (Fosc = 32 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-2: Idd, LP Oscillator Mode (Fosc = 32 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-3: Idd Typical, XT and EXTRC Oscillator, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-4: Idd Maximum, XT and EXTRC Oscillator, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-5: Idd Typical, XT and EXTRC Oscillator, PIC12F1822 and PIC16F1823 only
- FIGURE 31-6: Idd Maximum, XT and EXTRC Oscillator, PIC12F1822 and PIC16F1823 only
- FIGURE 31-7: Idd, EC Oscillator, Low-Power Mode (Fosc = 32 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-8: Idd, EC Oscillator, Low-Power Mode (Fosc = 32 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-9: Idd, EC Oscillator, Low-Power Mode (Fosc = 500 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-10: Idd, EC Oscillator, Low-Power Mode (Fosc = 500 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-11: Idd Typical, EC Oscillator, Medium-Power Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-12: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-13: Idd Typical, EC Oscillator, Medium-Power Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-14: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-15: Idd Typical, EC Oscillator, High-Power Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-16: Idd Maximum, EC Oscillator, High-Power Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-17: IddTypical, EC Oscillator, High-Power Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-18: Idd Maximum, EC Oscillator, High-Power Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-19: Idd, LFINTOSC Mode (Fosc = 32 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-20: Idd, LFINTOSC Mode (Fosc = 32 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-21: Idd, MFINTOSC Mode (Fosc = 500 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-22: Idd, MFINTOSC Mode (Fosc = 500 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-23: Idd Typical, HFINTOSC Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-24: Idd Maximum, HFINTOSC Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-25: Idd Typical, HFINTOSC Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-26: Idd Maximum, HFINTOSC Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-27: Idd Typical, HS Oscillator, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-28: Idd Maximum, HS Oscillator, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-29: Idd Typical, HS Oscillator, PIC12F1822 and PIC16F1823 only
- FIGURE 31-30: Idd Maximum, HS Oscillator, PIC12F1822 and PIC16F1823 only
- FIGURE 31-31: Ipd Base, Low-Power Sleep Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-32: Ipd Base, Low-Power Sleep Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-33: Ipd, Watchdog Timer (WDT), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-34: Ipd, Watchdog Timer (WDT), PIC12F1822 and PIC16F1823 only
- FIGURE 31-35: Ipd, Fixed Voltage Reference (FVR), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-36: Ipd, Fixed Voltage Reference (FVR), PIC12F1822 and PIC16F1823 only
- FIGURE 31-37: Ipd, Brown-Out Reset (BOR), PIC12F1822 and PIC16F1823 only
- FIGURE 31-38: Ipd, Timer1 Oscillator (Fosc = 32 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-39: Ipd, Timer1 Oscillator (Fosc = 32 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-40: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-41: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC12F1822 and PIC16F1823 only
- FIGURE 31-42: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-43: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC12F1822 and PIC16F1823 only
- FIGURE 31-44: POR Release Voltage
- FIGURE 31-45: POR Rearm Voltage, PIC12F1822 and PIC16F1823 only
- FIGURE 31-46: WDT Time-out Period
- FIGURE 31-47: PWRT Period
- FIGURE 31-48: Comparator Hysteresis, Normal-Power Mode (CxSP = 1, CxHYS = 1)
- FIGURE 31-49: Comparator Hysteresis, Low-Power Mode (CxSP = 0, CxHYS = 1)
- FIGURE 31-50: Comparator Response Time, Normal-Power Mode (CxSP = 1)
- FIGURE 31-51: Comparator Response Time over Temperature, Normal-Power Mode (CxSP = 1)
- FIGURE 31-52: Comparator Input Offset at 25°C, Normal-Power Mode (CxSP = 1), PIC12F1822 and PIC16F1823 Only
- 32.0 Development Support
- 32.1 MPLAB X Integrated Development Environment Software
- 32.2 MPLAB XC Compilers
- 32.3 MPASM Assembler
- 32.4 MPLINK Object Linker/ MPLIB Object Librarian
- 32.5 MPLAB Assembler, Linker and Librarian for Various Device Families
- 32.6 MPLAB X SIM Software Simulator
- 32.7 MPLAB REAL ICE In-Circuit Emulator System
- 32.8 MPLAB ICD 3 In-Circuit Debugger System
- 32.9 PICkit 3 In-Circuit Debugger/ Programmer
- 32.10 MPLAB PM3 Device Programmer
- 32.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
- 32.12 Third-Party Development Tools
- 33.0 Packaging Information
- Appendix A: Data Sheet Revision History
- Appendix B: Migrating From Other PIC® Devices
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Trademarks
- Worldwide Sales
PIC12(L)F1822/16(L)F1823
DS40001413E-page 292 2010-2015 Microchip Technology Inc.
FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
BAUDCON
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86
PIE1
TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87
PIR1
TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89
RCREG EUSART Receive Data Register 273*
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 278
SPBRGL BRG<7:0> 280*
SPBRGH BRG<15:8> 280*
TRISA
— —
TRISA5 TRISA4
TRISA3 TRISA2 TRISA1 TRISA0 117
TRISC
(1)
— —
TRISC5 TRISC4
TRISC3 TRISC2 TRISC1 TRISC0 121
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
* Page provides register information.
Note 1: PIC16(L)F1823 only.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)