Datasheet

PIC12(L)F1822/16(L)F1823
DS40001413E-page 238  2010-2015 Microchip Technology Inc.
25.5.3 SLAVE TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W
bit of the
SSP1STAT register is set. The received address is
loaded into the SSP1BUF register, and an ACK
pulse
is sent by the slave on the ninth bit.
Following the ACK
, slave hardware clears the CKP bit
and the SCL pin is held low (see
Section 25.5.6
“Clock Stretching”
for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
The transmit data must be loaded into the SSP1BUF
register which also loads the SSP1SR register. Then
the SCL pin should be released by setting the CKP bit
of the SSP1CON1 register. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time.
The ACK
pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSP1CON2
register. If ACKSTAT is set (not ACK
), then the data
transfer is complete. In this case, when the not ACK
is
latched by the slave, the slave goes Idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK
), the next transmit data must be loaded into
the SSP1BUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP1 interrupt is generated for each data transfer
byte. The SSP1IF bit must be cleared by software and
the SSP1STAT register is used to determine the status
of the byte. The SSP1IF bit is set on the falling edge of
the ninth clock pulse.
25.5.3.1 Slave Mode Bus Collision
A slave receives a Read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSP1CON3 register is set,
the BCL1IF bit of the PIRx register is set. Once a bus
collision is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCL1IF bit
to handle a slave bus collision.
25.5.3.2 7-bit Transmission
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish a standard transmission.
Figure 25-18 can be used as a reference to this list.
1. Master sends a Start condition on SDA and
SCL.
2. S bit of SSP1STAT is set; SSP1IF is set if inter-
rupt-on-Start detect is enabled.
3. Matching address with R/W
bit set is received by
the Slave setting SSP1IF bit.
4. Slave hardware generates an ACK
and sets
SSP1IF.
5. SSP1IF bit is cleared by user.
6. Software reads the received address from
SSP1BUF, clearing BF.
7. R/W
is set so CKP was automatically cleared
after the ACK.
8. The slave software loads the transmit data into
SSP1BUF.
9. CKP bit is set releasing SCL, allowing the
master to clock the data out of the slave.
10. SSP1IF is set after the ACK
response from the
master is loaded into the ACKSTAT register.
11. SSP1IF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
13. Steps 9-13 are repeated for each transmitted
byte.
14. If the master sends a not ACK
; the clock is not
held, but SSP1IF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
Note 1: If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.