Datasheet

 2010-2015 Microchip Technology Inc. DS40001413E-page 233
PIC12(L)F1822/16(L)F1823
25.5.2 SLAVE RECEPTION
When the R/W bit of a matching received address byte
is clear, the R/W
bit of the SSP1STAT register is
cleared. The received address is loaded into the
SSP1BUF register and acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSP1STAT
register is set, or bit SSP1OV of the SSP1CON1 regis-
ter is set. The BOEN bit of the SSP1CON3 register
modifies this operation. For more information see
Register 25-4.
An MSSP1 interrupt is generated for each transferred
data byte. Flag bit, SSP1IF, must be cleared by soft-
ware.
When the SEN bit of the SSP1CON2 register is set,
SCL will be held low (clock stretch) following each
received byte. The clock must be released by setting
the CKP bit of the SSP1CON1 register, except
sometimes in 10-bit mode. See
Section 25.2.3 “SPI
Master Mode”
for more detail.
25.5.2.1 7-bit Addressing Reception
This section describes a standard sequence of events
for the MSSP1 module configured as an I
2
C Slave in
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 25-14 and Figure 25-15 is used as a visual
reference for this description.
This is a step by step process of what typically must
be done to accomplish I
2
C communication.
1. Start bit detected.
2. S bit of SSP1STAT is set; SSP1IF is set if inter-
rupt on Start detect is enabled.
3. Matching address with R/W
bit clear is received.
4. The slave pulls SDA low sending an ACK
to the
master, and sets SSP1IF bit.
5. Software clears the SSP1IF bit.
6. Software reads received address from
SSP1BUF clearing the BF flag.
7. If SEN = 1; Slave software sets CKP bit to
release the SCL line.
8. The master clocks out a data byte.
9. Slave drives SDA low sending an ACK
to the
master, and sets SSP1IF bit.
10. Software clears SSP1IF.
11. Software reads the received byte from
SSP1BUF clearing BF.
12. Steps 8-12 are repeated for all received bytes
from the Master.
13. Master sends Stop condition, setting P bit of
SSP1STAT, and the bus goes Idle.
25.5.2.2 7-bit Reception with AHEN and
DHEN
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the eighth
falling edge of SCL. These additional interrupts allow
the slave software to decide whether it wants to ACK
the receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I
2
C communi-
cation. Figure 25-16 displays a module using both
address and data holding. Figure 25-17 includes the
operation with the SEN bit of the SSP1CON2 register
set.
1. S bit of SSP1STAT is set; SSP1IF is set if inter-
rupt on Start detect is enabled.
2. Matching address with R/W
bit clear is clocked
in. SSP1IF is set and CKP cleared after the 8th
falling edge of SCL.
3. Slave clears the SSP1IF.
4. Slave can look at the ACKTIM bit of the
SSP1CON3 register to determine if the SSP1IF
was after or before the ACK.
5. Slave reads the address value from SSP1BUF,
clearing the BF flag.
6. Slave sets ACK
value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
8. SSP1IF is set after an ACK
, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSP1IF.
11. SSP1IF set and CKP cleared after eighth falling
edge of SCL for a received data byte.
12. Slave looks at ACKTIM bit of SSP1CON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSP1BUF
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK
= 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
Note: SSP1IF is still set after the 9th falling edge
of SCL even if there is no clock stretching
and BF has been cleared. Only if NACK is
sent to Master is SSP1IF not set