Datasheet

PIC12(L)F1822/16(L)F1823
DS40001413E-page 196  2010-2015 Microchip Technology Inc.
24.3.2 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP1 module for standard PWM operation:
1. Disable the CCP1 pin output driver by setting
the associated TRIS bit.
2. Load the PR2 register with the PWM period
value.
3. Configure the CCP1 module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
4. Load the CCPR1L register and the DC1B1 bits
of the CCP1CON register, with the PWM duty
cycle value.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register. See Note below.
• Configure the T2CKPS bits of the T2CON
register with the Timer prescale value.
• Enable the Timer by setting the TMR2ON
bit of the T2CON register.
6. Enable PWM output pin:
• Wait until the Timer overflows and the
TMR2IF bit of the PIR1 register is set. See
Note below.
• Enable the CCP1 pin output driver by clear-
ing the associated TRIS bit.
24.3.3 PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 24-1.
EQUATION 24-1: PWM PERIOD
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
•TMR2 is cleared
• The CCP1 pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H.
24.3.4 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR1L register and
DC1B<1:0> bits of the CCP1CON register. The
CCPR1L contains the eight MSbs and the DC1B<1:0>
bits of the CCP1CON register contain the two LSbs.
CCPR1L and DC1B<1:0> bits of the CCP1CON
register can be written to at any time. The duty cycle
value is not latched into CCPR1H until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR1H
register is read-only.
Equation 24-2 is used to calculate the PWM pulse
width.
Equation 24-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 24-2: PULSE WIDTH
EQUATION 24-3: DUTY CYCLE RATIO
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (F
OSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR1H and
2-bit latch, then the CCP1 pin is cleared (see
Figure 24-4).
Note: In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
PWM Period PR21+4TOSC =
(TMR2 Prescale Value)
Note 1:
TOSC = 1/FOSC
Note: The Timer postscaler (see Section 22.1
“Timer2 Operation”
) is not used in the
determination of the PWM frequency.
Pulse Width CCPR1L:CCP1CON<5:4>  =
TOSC  (TMR2 Prescale Value)
Duty Cycle Ratio
CCPRxL:CCPxCON<5:4>
4 PRx 1+
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