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Table Of Contents

High-Performance RISC CPU
Flexible Oscillator Structure
Special Microcontroller Features
Extreme Low-Power Management PIC12LF1822/16LF1823 with XLP
Analog Features
Peripheral Highlights
Peripheral Features (Continued)
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- TABLE 1-1: Device Peripheral Summary
- FIGURE 1-1: PIC12(L)F1822/16(L)F1823 Block Diagram
- TABLE 1-2: PIC12(L)F1822 Pinout Description
- TABLE 1-3: PIC16(L)F1823 Pinout Description
2.0 Enhanced Mid-Range CPU
- 2.1 Automatic Interrupt Context Saving
- 2.2 16-Level Stack with Overflow and Underflow
- 2.3 File Select Registers
- 2.4 Instruction Set
  - FIGURE 2-1: Core Block Diagram
3.0 Memory Organization
- 3.1 Program Memory Organization
- 3.2 Data Memory Organization
- 3.3 PCL and PCLATH
- 3.4 Stack
  - 3.4.1 Accessing the Stack
  - 3.4.2 Overflow/Underflow Reset
- 3.5 Indirect Addressing
4.0 Device Configuration
- 4.1 Configuration Words
  - Register 4-1: Configuration Word 1
  - Register 4-2: Configuration Word 2
- 4.2 Code Protection
  - 4.2.1 Program Memory Protection
  - 4.2.2 Data EEPROM Protection
- 4.3 Write Protection
- 4.4 User ID
- 4.5 Device ID and Revision ID
  - Register 4-3: DEVICEID: Device ID Register(1)
5.0 Oscillator Module (With Fail-Safe Clock Monitor)
- 5.1 Overview
  - FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram
- 5.2 Clock Source Types
  - 5.2.1 External Clock Sources
  - 5.2.2 Internal Clock Sources
    - FIGURE 5-7: Internal Oscillator Switch Timing
- 5.3 Clock Switching
- 5.4 Two-Speed Clock Start-up Mode
- 5.5 Fail-Safe Clock Monitor
- 5.6 Oscillator Control Registers
6.0 Reference Clock Module
- 6.1 Slew Rate
- 6.2 Effects of a Reset
- 6.3 Conflicts with the CLKR pin
  - 6.3.1 Oscillator Modes
  - 6.3.2 CLKOUT Function
- 6.4 Operation During Sleep
7.0 Resets
- FIGURE 7-1: Simplified Block Diagram Of On-Chip Reset Circuit
- 7.1 Power-on Reset (POR)
  - 7.1.1 Power-up Timer (PWRT)
- 7.2 Brown-Out Reset (BOR)
- 7.3 MCLR
- 7.4 Watchdog Timer (WDT) Reset
- 7.5 RESET Instruction
- 7.6 Stack Overflow/Underflow Reset
- 7.7 Programming Mode Exit
- 7.8 Power-Up Timer
- 7.9 Start-up Sequence
  - FIGURE 7-4: Reset Start-Up Sequence
- 7.10 Determining the Cause of a Reset
  - TABLE 7-3: Reset Status Bits and Their Significance
  - TABLE 7-4: Reset Condition for Special Registers(2)
- 7.11 Power Control (PCON) Register
  - Register 7-2: PCON: Power Control Register
  - TABLE 7-5: Summary Of Registers Associated With Resets
8.0 Interrupts
- FIGURE 8-1: Interrupt Logic
- FIGURE 8-2: Peripheral Interrupt Logic
- 8.1 Operation
- 8.2 Interrupt Latency
  - FIGURE 8-3: Interrupt Latency
  - FIGURE 8-4: INT Pin Interrupt Timing
- 8.3 Interrupts During Sleep
- 8.4 INT Pin
- 8.5 Automatic Context Saving
9.0 Power-Down Mode (Sleep)
- 9.1 Wake-up from Sleep
  - 9.1.1 Wake-up Using Interrupts
    - FIGURE 9-1: Wake-Up From Sleep Through Interrupt
    - TABLE 9-1: Summary of Registers Associated with Power-Down Mode
10.0 Watchdog Timer
- FIGURE 10-1: Watchdog Timer Block Diagram
- 10.1 Independent Clock Source
- 10.2 WDT Operating Modes
- 10.3 Time-Out Period
- 10.4 Clearing the WDT
- 10.5 Operation During Sleep
  - TABLE 10-2: WDT Clearing Conditions
  - Register 10-1: WDTCON: Watchdog Timer Control Register
11.0 Data EEPROM and Flash Program Memory Control
- 11.1 EEADRL and EEADRH Registers
  - 11.1.1 EECON1 and EECON2 Registers
- 11.2 Using the Data EEPROM
- 11.3 Flash Program Memory Overview
- 11.4 Modifying Flash Program Memory
- 11.5 User ID, Device ID and Configuration Word Access
  - TABLE 11-2: User ID, Device ID and Configuration Word Access (CFGS = 1)
- 11.6 Write Verify
12.0 I/O Ports
- TABLE 12-1: Port Availability Per Device
- FIGURE 12-1: Generic I/O Port Operation
- 12.1 Alternate Pin Function
  - Register 12-1: APFCON: Alternate Pin Function Control Register
- 12.2 PORTA Registers
  - 12.2.1 ANSELA Register
    - EXAMPLE 12-1: Initializing PORTA
  - 12.2.2 PORTA Functions and Output Priorities
- 12.3 PORTC Registers (PIC16(L)F1823 only)
  - 12.3.1 ANSELC Register
    - EXAMPLE 12-2: Initializing PORTC
  - 12.3.2 PORTC Functions and Output Priorities
13.0 Interrupt-On-Change
- 13.1 Enabling the Module
- 13.2 Individual Pin Configuration
- 13.3 Interrupt Flags
- 13.4 Clearing Interrupt Flags
  - EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example)
- 13.5 Operation in Sleep
14.0 Fixed Voltage Reference (FVR)
- 14.1 Independent Gain Amplifiers
- 14.2 FVR Stabilization Period
15.0 Temperature Indicator Module
- 15.1 Circuit Operation
  - EQUATION 15-1: Vout Ranges
  - FIGURE 15-1: Temperature Circuit Diagram
- 15.2 Minimum Operating Vdd vs. Minimum Sensing Temperature
  - TABLE 15-1: Recommended Vdd vs. Range
- 15.3 Temperature Output
  - 15.3.1 ADC Acquisition Time
16.0 Analog-to-Digital Converter (ADC) Module
- FIGURE 16-1: ADC Block Diagram
- 16.1 ADC Configuration
- 16.2 ADC Operation
- 16.3 A/D Acquisition Requirements
17.0 Digital-to-Analog Converter (DAC) Module
- 17.1 Output Voltage Selection
  - EQUATION 17-1: DAC Output Voltage
- 17.2 Ratiometric Output Level
- 17.3 DAC Voltage Reference Output
  - FIGURE 17-1: Digital-to-Analog Converter Block Diagram
  - FIGURE 17-2: Voltage Reference Output Buffer Example
- 17.4 Low-Power Voltage State
  - 17.4.1 Output Clamped to Positive Voltage Source
  - 17.4.2 Output Clamped to Negative Voltage Source
    - FIGURE 17-3: Output Voltage Clamping Examples
- 17.5 Operation During Sleep
- 17.6 Effects of a Reset
18.0 SR Latch
- 18.1 Latch Operation
- 18.2 Latch Output
- 18.3 Effects of a Reset
19.0 Comparator Module
- 19.1 Comparator Overview
- 19.2 Comparator Control
- 19.3 Comparator Hysteresis
- 19.4 Timer1 Gate Operation
  - 19.4.1 Comparator Output Synchronization
- 19.5 Comparator Interrupt
- 19.6 Comparator Positive Input Selection
- 19.7 Comparator Negative Input Selection
- 19.8 Comparator Response Time
- 19.9 Interaction with ECCP Logic
- 19.10 Analog Input Connection Considerations
20.0 Timer0 Module
- 20.1 Timer0 Operation
21.0 Timer1 Module with Gate Control
- FIGURE 21-1: Timer1 Block Diagram
- 21.1 Timer1 Operation
  - TABLE 21-1: Timer1 Enable Selections
- 21.2 Clock Source Selection
  - 21.2.1 Internal Clock Source
  - 21.2.2 External Clock Source
    - TABLE 21-2: Clock Source Selections
- 21.3 Timer1 Prescaler
- 21.4 Timer1 Oscillator
- 21.5 Timer1 Operation in Asynchronous Counter Mode
  - 21.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode
- 21.6 Timer1 Gate
- 21.7 Timer1 Interrupt
- 21.8 Timer1 Operation During Sleep
- 21.9 ECCP/CCP Capture/Compare Time Base
- 21.10 ECCP/CCP Special Event Trigger
- 21.11 Timer1 Control Register
  - Register 21-1: T1CON: Timer1 Control Register
- 21.12 Timer1 Gate Control Register
  - Register 21-2: T1GCON: Timer1 Gate Control Register
  - TABLE 21-5: Summary of Registers Associated with Timer1
22.0 Timer2 Module
- FIGURE 22-1: Timer2 Block Diagram
- 22.1 Timer2 Operation
- 22.2 Timer2 Interrupt
- 22.3 Timer2 Output
- 22.4 Timer2 Operation During Sleep
  - Register 22-1: T2CON: Timer2 Control Register
  - TABLE 22-1: Summary of Registers Associated With Timer2
23.0 Data Signal Modulator
- FIGURE 23-1: Simplified Block Diagram of the Data Signal Modulator
- 23.1 DSM Operation
- 23.2 Modulator Signal Sources
- 23.3 Carrier Signal Sources
- 23.4 Carrier Synchronization
- 23.5 Carrier Source Polarity Select
- 23.6 Carrier Source Pin Disable
- 23.7 Programmable Modulator Data
- 23.8 Modulator Source Pin Disable
- 23.9 Modulated Output Polarity
- 23.10 Slew Rate Control
- 23.11 Operation in Sleep Mode
- 23.12 Effects of a Reset
24.0 Capture/Compare/PWM Modules
- TABLE 24-1: PWM Resources
- 24.1 Capture Mode
- 24.2 Compare Mode
- 24.3 PWM Overview
- 24.4 PWM (Enhanced Mode)
25.0 Master Synchronous Serial Port Module
- 25.1 Master SSP (MSSP1) Module Overview
- 25.2 SPI Mode Overview
- 25.3 I2C Mode Overview
- 25.4 I2C Mode Operation
- 25.5 I2C Slave Mode Operation
- 25.6 I2C Master Mode
- 25.7 Baud Rate Generator
26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- FIGURE 26-1: EUSART Transmit Block Diagram
- FIGURE 26-2: EUSART Receive Block Diagram
- 26.1 EUSART Asynchronous Mode
  - 26.1.1 EUSART Asynchronous Transmitter
  - 26.1.2 EUSART Asynchronous Receiver
    - FIGURE 26-5: Asynchronous Reception
    - TABLE 26-2: Summary of Registers Associated with Asynchronous Reception
- 26.2 Clock Accuracy with Asynchronous Operation
- 26.3 EUSART Baud Rate Generator (BRG)
- 26.4 EUSART Synchronous Mode
  - 26.4.1 Synchronous Master Mode
  - 26.4.2 Synchronous Slave Mode
    - TABLE 26-9: Summary of Registers Associated with Synchronous Slave Transmission
    - TABLE 26-10: Summary of Registers Associated with Synchronous Slave Reception
- 26.5 EUSART Operation During Sleep
27.0 Capacitive Sensing (CPS) Module
- FIGURE 27-1: Capacitive Sensing Block Diagram
- FIGURE 27-2: Capacitive Sensing Oscillator Block Diagram
- 27.1 Analog MUX
- 27.2 Capacitive Sensing Oscillator
- 27.3 Voltage References
- 27.4 Current Ranges
  - TABLE 27-1: Current Mode Selection
- 27.5 Timer Resources
- 27.6 Fixed Time Base
  - 27.6.1 Timer0
  - 27.6.2 Timer1
    - TABLE 27-2: Timer1 Enable Function
- 27.7 Software Control
- 27.8 Operation during Sleep
28.0 In-Circuit Serial Programming™ (ICSP™)
- 28.1 High-Voltage Programming Entry Mode
  - FIGURE 28-1: Vpp Limiter Example Circuit
- 28.2 Low-Voltage Programming Entry Mode
- 28.3 Common Programming Interfaces
29.0 Instruction Set Summary
- 29.1 Read-Modify-Write Operations
- 29.2 Instruction Descriptions
30.0 Electrical Specifications
- Absolute Maximum Ratings(†)
- 30.1 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended)
  - FIGURE 30-4: POR and POR Rearm with Slow Rising Vdd
- 30.2 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended)
- 30.3 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Power-Down)
- 30.4 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E
- 30.5 Memory Programming Requirements
- 30.6 Thermal Considerations
- 30.7 Timing Parameter Symbology
  - FIGURE 30-5: Load Conditions
- 30.8 AC Characteristics: PIC12(L)F1822/16(L)F1823-I/E
- 30.9 High Temperature Operation
31.0 DC and AC Characteristics Graphs and Charts
- FIGURE 31-1: Idd, LP Oscillator Mode (Fosc = 32 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-2: Idd, LP Oscillator Mode (Fosc = 32 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-3: Idd Typical, XT and EXTRC Oscillator, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-4: Idd Maximum, XT and EXTRC Oscillator, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-5: Idd Typical, XT and EXTRC Oscillator, PIC12F1822 and PIC16F1823 only
- FIGURE 31-6: Idd Maximum, XT and EXTRC Oscillator, PIC12F1822 and PIC16F1823 only
- FIGURE 31-7: Idd, EC Oscillator, Low-Power Mode (Fosc = 32 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-8: Idd, EC Oscillator, Low-Power Mode (Fosc = 32 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-9: Idd, EC Oscillator, Low-Power Mode (Fosc = 500 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-10: Idd, EC Oscillator, Low-Power Mode (Fosc = 500 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-11: Idd Typical, EC Oscillator, Medium-Power Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-12: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-13: Idd Typical, EC Oscillator, Medium-Power Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-14: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-15: Idd Typical, EC Oscillator, High-Power Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-16: Idd Maximum, EC Oscillator, High-Power Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-17: IddTypical, EC Oscillator, High-Power Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-18: Idd Maximum, EC Oscillator, High-Power Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-19: Idd, LFINTOSC Mode (Fosc = 32 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-20: Idd, LFINTOSC Mode (Fosc = 32 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-21: Idd, MFINTOSC Mode (Fosc = 500 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-22: Idd, MFINTOSC Mode (Fosc = 500 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-23: Idd Typical, HFINTOSC Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-24: Idd Maximum, HFINTOSC Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-25: Idd Typical, HFINTOSC Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-26: Idd Maximum, HFINTOSC Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-27: Idd Typical, HS Oscillator, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-28: Idd Maximum, HS Oscillator, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-29: Idd Typical, HS Oscillator, PIC12F1822 and PIC16F1823 only
- FIGURE 31-30: Idd Maximum, HS Oscillator, PIC12F1822 and PIC16F1823 only
- FIGURE 31-31: Ipd Base, Low-Power Sleep Mode, PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-32: Ipd Base, Low-Power Sleep Mode, PIC12F1822 and PIC16F1823 only
- FIGURE 31-33: Ipd, Watchdog Timer (WDT), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-34: Ipd, Watchdog Timer (WDT), PIC12F1822 and PIC16F1823 only
- FIGURE 31-35: Ipd, Fixed Voltage Reference (FVR), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-36: Ipd, Fixed Voltage Reference (FVR), PIC12F1822 and PIC16F1823 only
- FIGURE 31-37: Ipd, Brown-Out Reset (BOR), PIC12F1822 and PIC16F1823 only
- FIGURE 31-38: Ipd, Timer1 Oscillator (Fosc = 32 kHz), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-39: Ipd, Timer1 Oscillator (Fosc = 32 kHz), PIC12F1822 and PIC16F1823 only
- FIGURE 31-40: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-41: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC12F1822 and PIC16F1823 only
- FIGURE 31-42: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC12LF1822 and PIC16LF1823 only
- FIGURE 31-43: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC12F1822 and PIC16F1823 only
- FIGURE 31-44: POR Release Voltage
- FIGURE 31-45: POR Rearm Voltage, PIC12F1822 and PIC16F1823 only
- FIGURE 31-46: WDT Time-out Period
- FIGURE 31-47: PWRT Period
- FIGURE 31-48: Comparator Hysteresis, Normal-Power Mode (CxSP = 1, CxHYS = 1)
- FIGURE 31-49: Comparator Hysteresis, Low-Power Mode (CxSP = 0, CxHYS = 1)
- FIGURE 31-50: Comparator Response Time, Normal-Power Mode (CxSP = 1)
- FIGURE 31-51: Comparator Response Time over Temperature, Normal-Power Mode (CxSP = 1)
- FIGURE 31-52: Comparator Input Offset at 25°C, Normal-Power Mode (CxSP = 1), PIC12F1822 and PIC16F1823 Only
32.0 Development Support
- 32.1 MPLAB X Integrated Development Environment Software
- 32.2 MPLAB XC Compilers
- 32.3 MPASM Assembler
- 32.4 MPLINK Object Linker/ MPLIB Object Librarian
- 32.5 MPLAB Assembler, Linker and Librarian for Various Device Families
- 32.6 MPLAB X SIM Software Simulator
- 32.7 MPLAB REAL ICE In-Circuit Emulator System
- 32.8 MPLAB ICD 3 In-Circuit Debugger System
- 32.9 PICkit 3 In-Circuit Debugger/ Programmer
- 32.10 MPLAB PM3 Device Programmer
- 32.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
- 32.12 Third-Party Development Tools
33.0 Packaging Information
- 33.1 Package Marking Information
- 33.1 Package Marking Information (Continuation)
  - TABLE 33-1: 8-Lead 3x3x0.9 DFN (MF) Top Marking
  - TABLE 33-2: 8-Lead 3x3x0.5 uDFN (rF) Top Marking
- 33.1 Package Marking Information (Continuation)
- 33.1 Package Marking Information (Continuation)
- 33.2 Package Details
Appendix A: Data Sheet Revision History
Appendix B: Migrating From Other PIC® Devices
- TABLE B-1: Feature Comparison
The Microchip Web Site
Customer Change Notification Service
Customer Support
Product Identification System
Trademarks
Worldwide Sales

 2010-2015 Microchip Technology Inc. DS40001413E-page 151

PIC12(L)F1822/16(L)F1823

TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

on Page

ANSELA

— — —ANSA4— ANSA2 ANSA1 ANSA0

118

SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 149

SRCON1 SRSPE SRSCKE SRSC2E

(1)

SRSC1E SRRPE SRRCKE SRRC2E

(1)

SRRC1E 150

TRISA

— —TRISA5TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

117

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module.

Note 1: PIC16(L)F1823 only.