Datasheet

 2011 Microchip Technology Inc. Preliminary DS041441B-page 375
PIC12(L)F1840
Associated Registers
Receive..................................................... 293
Transmit.................................................... 292
Reception.......................................................... 293
Transmission .................................................... 292
Extended Instruction Set
ADDFSR ................................................................... 311
F
Fail-Safe Clock Monitor....................................................... 59
Fail-Safe Condition Clearing....................................... 59
Fail-Safe Detection ..................................................... 59
Fail-Safe Operation..................................................... 59
Reset or Wake-up from Sleep..................................... 59
Firmware Instructions........................................................ 307
Fixed Voltage Reference (FVR)........................................ 123
Associated Registers ................................................ 124
Flash Program Memory ...................................................... 97
Erasing...................................................................... 102
Modifying................................................................... 106
Writing....................................................................... 102
FSR Register ................ 24, 25, 26, 27, 28, 29, 30, 31, 32, 33
FVRCON (Fixed Voltage Reference Control) Register..... 124
I
I
2
C Mode (MSSPx)
Acknowledge Sequence Timing................................ 251
Bus Collision
During a Repeated Start Condition................... 256
During a Stop Condition.................................... 257
Effects of a Reset...................................................... 252
I
2
C Clock Rate w/BRG.............................................. 259
Master Mode
Operation .......................................................... 243
Reception.......................................................... 249
Start Condition Timing .............................. 245, 246
Transmission .................................................... 247
Multi-Master Communication, Bus Collision and
Arbitration ......................................................... 252
Multi-Master Mode .................................................... 252
Read/Write Bit Information (R/W
Bit) ........................ 228
Slave Mode
Transmission .................................................... 233
Sleep Operation ........................................................ 252
Stop Condition Timing............................................... 251
INDF Register ............... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33
Indirect Addressing .............................................................37
Instruction Format............................................................. 308
Instruction Set ................................................................... 307
ADDLW..................................................................... 311
ADDWF..................................................................... 311
ADDWFC .................................................................. 311
ANDLW..................................................................... 311
ANDWF..................................................................... 311
BRA........................................................................... 312
CALL......................................................................... 313
CALLW...................................................................... 313
LSLF ......................................................................... 315
LSRF......................................................................... 315
MOVF........................................................................ 315
MOVIW ..................................................................... 316
MOVLB ..................................................................... 316
MOVWI ..................................................................... 317
OPTION .................................................................... 317
RESET...................................................................... 317
SUBWFB................................................................... 319
TRIS ......................................................................... 320
BCF .......................................................................... 312
BSF........................................................................... 312
BTFSC...................................................................... 312
BTFSS...................................................................... 312
CALL......................................................................... 313
CLRF ........................................................................ 313
CLRW ....................................................................... 313
CLRWDT .................................................................. 313
COMF ....................................................................... 313
DECF........................................................................ 313
DECFSZ ................................................................... 314
GOTO....................................................................... 314
INCF ......................................................................... 314
INCFSZ..................................................................... 314
IORLW...................................................................... 314
IORWF...................................................................... 314
MOVLW.................................................................... 316
MOVWF.................................................................... 316
NOP.......................................................................... 317
RETFIE..................................................................... 318
RETLW..................................................................... 318
RETURN................................................................... 318
RLF........................................................................... 318
RRF .......................................................................... 319
SLEEP...................................................................... 319
SUBLW..................................................................... 319
SUBWF..................................................................... 319
SWAPF..................................................................... 320
XORLW .................................................................... 320
XORWF .................................................................... 320
INTCON Register................................................................ 83
Internal Oscillator Block
INTOSC
Specifications ................................................... 337
Internal Sampling Switch (R
SS) Impedance ..................... 137
Internet Address ............................................................... 379
Interrupt-On-Change......................................................... 119
Associated Registers................................................ 121
Interrupts ............................................................................ 77
ADC .......................................................................... 132
Associated registers w/ Interrupts .............................. 88
Configuration Word w/ Clock Sources........................ 63
Configuration Word w/ Reference Clock Sources ...... 67
TMR1........................................................................ 167
INTOSC Specifications ..................................................... 337
IOCAF Register ................................................................ 120
IOCAN Register................................................................ 120
IOCAP Register ................................................................ 120
L
LATA Register .................................................................. 116
Load Conditions................................................................ 335
LSLF ................................................................................. 315
LSRF ................................................................................ 315
M
Master Synchronous Serial Port. See MSSPx
MCLR
................................................................................. 72
Internal........................................................................ 72
MDCARH Register............................................................ 186
MDCARL Register ............................................................ 187
MDCON Register.............................................................. 184
MDSRC Register .............................................................. 185
Memory Organization ......................................................... 15
Data ............................................................................ 17