Datasheet

PIC12(L)F1840
DS41441B-page 258 Preliminary  2011 Microchip Technology Inc.
TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 84
PIE2
OSFIE — C1IE EEIE BCL1IE
—
— — 85
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
86
PIR2
OSFIF
—
C1IF EEIF BCL1IF — —
— 87
SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 264
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 215*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 261
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 262
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 263
SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 264
SSP1STAT SMP CKE
D/A P S R/W UA BF 260
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 115
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I
2
C™ mode.
* Page provides register information.