Datasheet

 2011 Microchip Technology Inc. Preliminary DS41441B-page 173
PIC12(L)F1840
TABLE 21-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0
116
CCP1CON
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
207
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
83
PIE1 TMR1GIE
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
84
PIR1 TMR1GIF
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
86
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
167*
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
167*
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 115
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—TMR1ON
171
T1GCON
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS1 T1GSS0
172
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
* Page provides register information.