Datasheet

 2011 Microchip Technology Inc. Preliminary DS41441B-page 5
PIC12(L)F1840
FIGURE 1: 8-PIN DIAGRAM FOR PIC12(L)F1840
TABLE 1: 8-PIN ALLOCATION TABLE (PIC12(L)F1840)
I/O
8-Pin PDIP/SOIC/DFN
A/D
Reference
Cap Sense
Comparator
SR Latch
Timers
ECCP
EUSART
MSSP
Interrupt
Modulator
Pull-up
Basic
RA0
7 AN0 DACOUT CPS0 C1IN+ — — P1B
(1)
TX
(1)
CK
(1)
SDO
(1)
SS
(1)
IOC MDOUT Y ICSPDAT
ICDDAT
RA1
6AN1 VREF CPS1 C1IN0- SRI — — RX
(1)
DT
(1)
SCL
SCK
IOC MDMIN Y ICSPCLK
ICPCLK
RA2
5 AN2 — CPS2 C1OUT SRQ T0CKI CCP1
(1)
P1A
(1)
FLT0
— SDA
SDI
INT/
IOC
MDCIN1 Y —
RA3
4—————T1G
(1)
——
SS
(1)
IOC — Y
MCLR
VPP
RA4
3 AN3 — CPS3 C1IN1- — T1G
(1)
T1OSO
P1B
(1)
TX
(1)
CK
(1)
SDO
(1)
IOC MDCIN2 Y OSC2
CLKOUT
CLKR
RA5
2 — — — — SRNQ T1CKI
T1OSI
CCP1
(1)
P1A
(1)
RX
(1)
DT
(1)
— IOC — Y OSC1
CLKIN
VDD
1 — — — — — — — — — — — — VDD
VSS
8————————————VSS
Note 1: Pin function is selectable via the APFCON register.
PDIP, SOIC, DFN
1
2
3
4
8
7
6
5
VDD
RX
(1)
/DT
(1)
/CCP1
(1)
/P1A
(1)
/SRNQ/T1CKI/T1OSI/OSC1/CLKIN/RA5
MDCIN2/T1G
(1)
/P1B
(1)
/TX
(1)
/CK
(1)
/SDO
(1)
/CLKR/C1IN1-/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4
MCLR
/VPP/T1G
(1)
/SS
(1)
/RA3
V
SS
RA0/AN0/CPS0/C1IN+/DACOUT/TX
(1)
/CK
(1)
/SDO
(1)
/SS
(1)
/P1B
(1)
/MDOUT/ICSPDAT
RA1/AN1/CPS1/V
REF/C1IN0-/SRI/RX
(1)
/DT
(1)
/SCL/SCK/MDMIN/ICSPCLK
RA2/AN2/CPS2/C1OUT/SRQ/T0CKI/CCP1
(1)
/P1A
(1)
/FLT0/SDA/SDI/INT/MDCIN1
Note 1: Pin function is selectable via the APFCON register.
PIC12(L)F1840