Datasheet

PIC12(L)F1840
DS041441B-page 378 Preliminary  2011 Microchip Technology Inc.
Baud Rate Generator with Clock Arbitration ............. 244
BRG Reset Due to SDA Arbitration During Start
Condition........................................................... 255
Brown-out Reset (BOR) ............................................ 340
Brown-out Reset Situations ........................................ 71
Bus Collision During a Repeated Start Condition
(Case 1) ............................................................ 256
Bus Collision During a Repeated Start Condition
(Case 2) ............................................................ 256
Bus Collision During a Start Condition (SCL = 0) .....255
Bus Collision During a Stop Condition (Case 1) .......257
Bus Collision During a Stop Condition (Case 2) .......257
Bus Collision During Start Condition (SDA only) ...... 254
Bus Collision for Transmit and Acknowledge............ 253
CLKOUT and I/O....................................................... 338
Clock Synchronization ..............................................241
Clock Timing ............................................................. 336
Comparator Output ...................................................151
Enhanced Capture/Compare/PWM (ECCP) ............. 343
Fail-Safe Clock Monitor (FSCM) .................................60
First Start Bit Timing .................................................245
Half-Bridge PWM Output .................................. 200, 203
I
2
C Bus Data.............................................................351
I
2
C Bus Start/Stop Bits..............................................350
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 248
I
2
C Master Mode (7-Bit Reception)........................... 250
I
2
C Stop Condition Receive or Transmit Mode ......... 252
INT Pin Interrupt.......................................................... 81
Internal Oscillator Switch Timing.................................55
PWM Auto-shutdown ................................................ 202
Firmware Restart .............................................. 201
PWM Output (Active-High)........................................199
PWM Output (Active-Low) ........................................199
Repeat Start Condition.............................................. 246
Reset Start-up Sequence............................................73
Reset, WDT, OST and Power-up Timer ................... 339
Send Break Character Sequence ............................. 287
SPI Master Mode (CKE = 1, SMP = 1) .....................348
SPI Mode (Master Mode) .......................................... 218
SPI Slave Mode (CKE = 0) ....................................... 349
SPI Slave Mode (CKE = 1) ....................................... 349
Synchronous Reception (Master Mode, SREN) ....... 291
Synchronous Transmission....................................... 289
Synchronous Transmission (Through TXEN) ........... 289
Timer0 and Timer1 External Clock ...........................342
Timer1 Incrementing Edge........................................167
Two Speed Start-up ....................................................58
USART Synchronous Receive (Master/Slave) ......... 347
USART Synchronous Transmission (Master/Slave) . 346
Wake-up from Interrupt ............................................... 90
Timing Diagrams and Specifications
PLL Clock..................................................................337
Timing Parameter Symbology...........................................335
Timing Requirements
I
2
C Bus Data.............................................................352
SPI Mode .................................................................. 350
TMR0 Register.................................................................... 24
TMR1H Register ................................................................. 24
TMR1L Register.................................................................. 24
TMR2 Register.................................................................... 24
TRIS..................................................................................320
TRISA Register ........................................................... 25, 115
Two-Speed Clock Start-up Mode ........................................ 57
TXREG..............................................................................269
TXREG Register .................................................................27
TXSTA Register.......................................................... 27, 276
BRGH Bit .................................................................. 279
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 347
Requirements, Synchronous Transmission...... 347
Timing Diagram, Synchronous Receive ........... 347
Timing Diagram, Synchronous Transmission... 346
V
VREF. SEE ADC Reference Voltage
VREGCON Register ........................................................... 91
W
Wake-up on Break............................................................ 285
Wake-up Using Interrupts ................................................... 90
Watchdog Timer (WDT)...................................................... 72
Modes ......................................................................... 94
Specifications ........................................................... 341
WCOL ....................................................... 244, 247, 249, 251
WCOL Status Flag.................................... 244, 247, 249, 251
WDTCON Register ............................................................. 95
WPUB Register................................................................. 117
Write Protection .................................................................. 45
WWW Address ................................................................. 379
WWW, On-Line Support ....................................................... 7