Datasheet

PIC12(L)F1840
DS41441B-page 302 Preliminary  2011 Microchip Technology Inc.
TABLE 27-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — CPSCH<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-2 Unimplemented: Read as ‘0’
bit 1-0 CPSCH<1:0>: Capacitive Sensing Channel Select bits
If CPSON =
0:
These bits are ignored. No channel is selected.
If CPSON = 1:
00 = channel 0, (CPS0)
01 = channel 1, (CPS1)
10 = channel 2, (CPS2)
11 = channel 3, (CPS3)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELA
— — —ANSA4— ANSA2 ANSA1 ANSA0
116
CPSCON0 CPSON
CPSRM — — CPSRNG1 CPSRNG0 CPSOUT T0XCS
301
CPSCON1
— — — — — — CPSCH1 CPSCH0
302
INTCON GIE PEIE TMR0IE
INTE IOCIE TMR0IF INTF IOCIF
83
OPTION_REG
WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 161
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—TMR1ON
171
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
115
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the CPS module.