Datasheet

PIC12(L)F1840
DS41441B-page 206 Preliminary  2011 Microchip Technology Inc.
24.4.7 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
reset, see Section 12.1 “Alternate Pin Function” for
more information.
TABLE 24-9: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON
RXDTSEL SDOSEL SSSEL
—
T1GSEL TXCKSEL P1BSEL CCP1SEL
112
CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0>
207
CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0>
208
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
83
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
84
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
86
PR2
Timer2 Period Register 175*
PSTR1CON
— — — STR1SYNC Reserved Reserved STR1B STR1A
209
PWM1CON P1RSEN P1DC<6:0>
209
T2CON
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0>
177
TMR2 Timer2 Module Register
175
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
115
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
* Page provides register information.