Datasheet

 2011 Microchip Technology Inc. Preliminary DS41441B-page 193
PIC12(L)F1840
24.2.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
reset, see Section 12.1 “Alternate Pin Function” for
more information.
TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON
RXDTSEL SDOSEL SSSEL
—
T1GSEL TXCKSEL P1BSEL CCP1SEL
112
CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0>
207
CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB)
190
CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB)
190
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
83
PIE1 TMR1GIE
ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
84
PIE2
OSFIE
—
C1IE EEIE BCL1IE — — —
85
PIR1 TMR1GIF
ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
86
PIR2
OSFIF
—
C1IF EEIF BCL1IF — — —
87
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
—TMR1ON
171
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0>
172
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
167*
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
167*
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
115
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
* Page provides register information.