Datasheet

PIC12(L)F1840
DS41441B-page 112 Preliminary  2011 Microchip Technology Inc.
REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
RXDTSEL SDOSEL SSSEL
—
T1GSEL TXCKSEL P1BSEL CCP1SEL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 RXDTSEL: Pin Selection bit
0 = RX/DT function is on RA1
1 = RX/DT function is on RA5
bit 6 SDOSEL: Pin Selection bit
0 = SDO function is on RA0
1 = SDO function is on RA4
bit 5 SSSEL: Pin Selection bit
0 =SS
function is on RA3
1 =SS
function is on RA0
bit 4 Unimplemented: Read as ‘0’
bit 3 T1GSEL: Pin Selection bit
0 = T1G function is on RA4
1 = T1G function is on RA3
bit 2 TXCKSEL: Pin Selection bit
0 = TX/CK function is on RA0
1 = TX/CK function is on RA4
bit 1 P1BSEL: Pin Selection bit
0 = P1B function is on RA0
1 = P1B function is on RA4
bit 0 CCP1SEL: Pin Selection bit
0 = CCP1/P1A function is on RA2
1 = CCP1/P1A function is on RA5