PIC12(L)F1840 Data Sheet 8-Pin Flash Microcontrollers with nanoWatt XLP Technology 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC12(L)F1840 8-Pin Flash Microcontrollers with nanoWatt XLP Technology High-Performance RISC CPU: Low-Power Features: • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 32 MHz oscillator/clock input - DC – 125 ns instruction cycle • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset • Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) -
PIC12(L)F1840 Peripheral Features (Continued): • Data Signal Modulator module: - Selectable modulator and carrier sources • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications PIC12(L)F1840 Family Types DS41441B-page 4 I/O’s(1) 10-bit ADC (ch) CapSense (ch) Comparators Timers (8/16-bit) EUSART MSSP ECCP (Full-Bridge) ECCP (Half-Bridge) SR Latch PIC12LF1840 4K 256 PIC12F1840 4K 256 Note 1: One pin is input only.
8-PIN DIAGRAM FOR PIC12(L)F1840 PDIP, SOIC, DFN VDD 1 RX(1)/DT(1)/CCP1(1)/P1A(1)/SRNQ/T1CKI/T1OSI/OSC1/CLKIN/RA5 2 MDCIN2/T1G(1)/P1B(1)/TX(1)/CK(1)/SDO(1)/CLKR/C1IN1-/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 3 MCLR/VPP/T1G(1)/SS(1)/RA3 4 Note 8 VSS 7 RA0/AN0/CPS0/C1IN+/DACOUT/TX(1)/CK(1)/SDO(1)/SS(1)/P1B(1)/MDOUT/ICSPDAT 6 RA1/AN1/CPS1/VREF/C1IN0-/SRI/RX(1)/DT(1)/SCL/SCK/MDMIN/ICSPCLK 5 RA2/AN2/CPS2/C1OUT/SRQ/T0CKI/CCP1(1)/P1A(1)/FLT0/SDA/SDI/INT/MDCIN1 Pin function is selectable via the APFCON regi
PIC12(L)F1840 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13 3.0 Memory Organization ................................................................................
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PIC12(L)F1840 NOTES: DS41441B-page 8 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 1.0 DEVICE OVERVIEW The PIC12(L)F1840 are described within this data sheet. They are available in 8-pin packages. Figure 1-1 shows a block diagram of the PIC12(L)F1840 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC12(L)F1840 FIGURE 1-1: PIC12(L)F1840 BLOCK DIAGRAM Program Flash Memory CLKR OSC2/CLKOUT EEPROM RAM Clock Reference Timing Generation OSC1/CLKIN PORTA CPU INTRC Oscillator (Figure 2-1) MCLR Note 1: 2: DS41441B-page 10 SR Latch Timer0 Timer1 ADC 10-Bit DAC Comparators ECCP1 MSSP Modulator EUSART FVR CapSense See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 TABLE 1-2: PIC12(L)F1840 PINOUT DESCRIPTION Name Function Input Type RA0/AN0/CPS0/C1IN+/ DACOUT/TX(1)/CK(1)/SDO(1)/ SS(1)/P1B(1)/MDOUT/ICSPDAT/ ICDDAT RA0 TTL AN0 AN RA1/AN1/CPS1/VREF/C1IN0-/ SRI/RX(1)/DT(1)/SCL/SCK/ MDMIN/ICSPCLK/ICDCLK RA2/AN2/CPS2/C1OUT/SRQ/ T0CKI/CCP1(1)/P1A(1)/FLT0/ SDA/SDI/INT/MDCIN1 RA3/SS(1)/T1G(1)/VPP/MCLR Output Type Description CMOS General purpose I/O. — A/D Channel 0 input. CPS0 AN — Capacitive sensing input 0.
PIC12(L)F1840 TABLE 1-2: PIC12(L)F1840 PINOUT DESCRIPTION (CONTINUED) Name Function Input Type RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/C1IN1-/CLKR/ SDO(1)/CK(1)/TX(1)/P1B(1)/ T1G(1)/MDCIN2 RA4 TTL Output Type Description CMOS General purpose I/O. AN3 AN — CPS3 AN — A/D Channel 3 input. OSC2 — XTAL CLKOUT — T1OSO XTAL XTAL C1IN1- AN — CLKR — CMOS Clock Reference output. SDO — CMOS SPI data output. CK ST CMOS USART synchronous clock. TX — CMOS USART asynchronous transmit.
PIC12(L)F1840 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC12(L)F1840 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator S
PIC12(L)F1840 3.0 MEMORY ORGANIZATION There are three types of memory in PIC12(L)F1840 devices: Data Memory, Program Memory and Data EEPROM Memory(1). • Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM - Device Memory Maps - Special Function Registers Summary • Data EEPROM memory(1) The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.
PIC12(L)F1840 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC12(L)F1840 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE On-chip Program Memory 15 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.
PIC12(L)F1840 3.1.1.2 Indirect Read with FSR 3.2.1 The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
PIC12(L)F1840 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC12(L)F1840 3.2.2 3.2.5 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: GENERAL PURPOSE RAM There are up to 80 bytes of GPR in each data memory bank. 3.2.3.
PIC12(L)F1840 MEMORY MAP, BANKS 0-7 BANK 0 Preliminary 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA — — — — PIR1 PIR2 — — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON — CPSCON0 CPSCON1 BANK 1 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h
2011 Microchip Technology Inc.
PIC12(L)F1840 MEMORY MAP, BANKS 24-31 BANK 24 Preliminary C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 25 C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h
PIC12(L)F1840 TABLE 3-6: PIC12(L)F1840 MEMORY MAP, BANK 31 Bank 31 FA0h 3.2.6 The Special Function Register Summary for the device family are as follows: Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: SPECIAL FUNCTION REGISTERS SUMMARY Device STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — PIC12(L)F1840 STKPTR TOSL TOSH Bank(s) Page No.
PIC12(L)F1840 TABLE 3-7: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 000h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h(1) PCL Program Counter (PC) Least Signif
PIC12(L)F1840 TABLE 3-7: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 1 080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 082h(1) PCL Program Counter (PC)
PIC12(L)F1840 TABLE 3-7: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 102h(1) PCL Program Counter (PC)
PIC12(L)F1840 TABLE 3-7: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 182h(1) PCL Program Counter (PC)
PIC12(L)F1840 TABLE 3-7: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 202h(1) PCL Program Counter (PC)
PIC12(L)F1840 TABLE 3-7: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 5 280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 282h(1) PCL Program Counter (PC)
PIC12(L)F1840 TABLE 3-7: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 6 300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 302h(1) PCL Program Counter (PC)
PIC12(L)F1840 TABLE 3-7: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 382h(1) PCL Program Counter (PC)
PIC12(L)F1840 TABLE 3-7: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Banks 8-30 x00h/ x80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(1) PCL
PIC12(L)F1840 TABLE 3-7: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 31 F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(1) PCL Program Counter (PC)
PIC12(L)F1840 3.3 3.3.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC.
PIC12(L)F1840 3.4 3.4.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.
PIC12(L)F1840 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC12(L)F1840 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.
PIC12(L)F1840 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41441B-page 38 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC12(L)F1840 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC12(L)F1840 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers.
PIC12(L)F1840 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD CP bit 13 bit 7 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 R/P-1/1 MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0 bit 6 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is c
PIC12(L)F1840 REGISTER 4-1: bit 2-0 Note 1: 2: 3: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.
PIC12(L)F1840 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1/1 R/P-1/1 U-1 R/P-1/1 R/P-1/1 R/P-1/1 U-1 LVP DEBUG(2) — BORV STVREN PLLEN — bit 13 bit 7 U-1 U-1 R-1 U-1 U-1 R/P-1/1 R/P-1/1 — — Reserved — — WRT1 WRT0 bit 6 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared P = Programmable bit bit 13 LVP: Low-Volt
PIC12(L)F1840 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1.
PIC12(L)F1840 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.
PIC12(L)F1840 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits.
PIC12(L)F1840 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Oscillator Timer1 FOSC<2:0> = 100 T1OSO IRCF<3:0> HFPLL 500 kHz Source 16 MHz (HFINTOSC) Postscaler Internal Oscillator Block 500 kHz (MFINTOSC) 31 kHz Source 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.
PIC12(L)F1840 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained internally within the oscillator module.
PIC12(L)F1840 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 Note 1: 2: C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep RP(3) OSC2/CLKOUT RF(2) C2 Ceramic RS(1) Resonator A series resistor (RS) may be required for quartz crystals with low drive level. Note 1: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
PIC12(L)F1840 5.2.1.5 5.2.1.6 TIMER1 Oscillator External RC Mode The Timer1 Oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required.
PIC12(L)F1840 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<2:0> bits in Configuration Word 1 to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.
PIC12(L)F1840 5.2.2.3 Internal Oscillator Frequency Adjustment 5.2.2.5 The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number.
PIC12(L)F1840 5.2.2.6 32 MHz Internal Oscillator Frequency Selection 5.2.2.7 The Internal Oscillator Block can be used with the 4X PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: • The FOSC bits in Configuration Word 1 must be set to use the INTOSC source as the device system clock (FOSC<2:0> = 100).
PIC12(L)F1840 FIGURE 5-7: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC
PIC12(L)F1840 5.3 5.3.3 Clock Switching TIMER1 OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins.
PIC12(L)F1840 5.4 5.4.1 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
PIC12(L)F1840 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
PIC12(L)F1840 5.5 5.5.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word 1. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC).
PIC12(L)F1840 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: DS41441B-page 60 Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 5.
PIC12(L)F1840 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator i
PIC12(L)F1840 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = • • • 000001 = 000000
PIC12(L)F1840 NOTES: DS41441B-page 64 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 6.0 REFERENCE CLOCK MODULE 6.3 Conflicts with the CLKR pin The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR) and provide a secondary internal clock source to the modulator module. This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application.
PIC12(L)F1840 REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0 CLKRDIV2 CLKRDIV1 CLKRDIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 = Reference c
PIC12(L)F1840 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Name CLKRCON Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0 CLKRDIV2 CONFIG1 Legend: Bit 0 CLKRDIV1 CLKRDIV0 Register on Page 66 — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.
PIC12(L)F1840 NOTES: DS41441B-page 68 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 7.0 RESETS There are multiple ways to reset this device: • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 7-1.
PIC12(L)F1840 7.1 Power-on Reset (POR) 7.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC12(L)F1840 FIGURE 7-2: BROWN-OUT READY SBOREN TBORRDY BORRDY FIGURE 7-3: BOR Protection Active BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC12(L)F1840 7.3 MCLR 7.8 Power-Up Timer The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Word 1 and the LVP bit of Configuration Word 2 (Table 7-2). The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. TABLE 7-2: The Power-up Timer is controlled by the PWRTE bit of Configuration Word 1.
PIC12(L)F1840 FIGURE 7-4: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2011 Microchip Technology Inc.
PIC12(L)F1840 7.10 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 7-3 and Table 7-4 show the Reset conditions of these registers.
PIC12(L)F1840 7.11 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUNF) MCLR Reset (RMCLR) The PCON register bits are shown in Register 7-2.
PIC12(L)F1840 TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN — — — — — — BORRDY 71 PCON STKOVF STKUNF — — RMCLR RI POR BOR 75 STATUS — — — TO PD Z DC C 18 WDTCON — — SWDTEN 95 WDTPS<4:0> Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
PIC12(L)F1840 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce Interrupts. Refer to the corresponding chapters for details.
PIC12(L)F1840 FIGURE 8-2: PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE To Interrupt Logic (Figure 8-1) TMR2IF TMR2IE EEIF EEIE C1IF C1IE OSFIF OSFIE BCLIF BCLIE DS41441B-page 78 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 8.1 Operation 8.2 Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register) Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins.
PIC12(L)F1840 FIGURE 8-3: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NO
PIC12(L)F1840 FIGURE 8-4: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) PC + 1 — Dummy Cycle Inst (PC) 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1).
PIC12(L)F1840 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC12(L)F1840 8.5.1 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 8-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register.
PIC12(L)F1840 8.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 8-2. REGISTER 8-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC12(L)F1840 8.5.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 8-3. REGISTER 8-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC12(L)F1840 8.5.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 8-4. REGISTER 8-4: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC12(L)F1840 8.5.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 8-5. REGISTER 8-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC12(L)F1840 TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 161 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 84 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 86 PIR2 OSFIF — C1IF EEIF BCL1IF — — — 87
PIC12(L)F1840 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. WDT will be cleared but keeps running, if enabled for operation during Sleep. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5.
PIC12(L)F1840 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared.
PIC12(L)F1840 9.2 9.2.2 Low Power Sleep Mode Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the normal power mode when those peripherals are enabled. The LowPower Sleep mode is intended for use with these peripherals: The PIC12F1840 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.
PIC12(L)F1840 TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 120 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 120 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 120 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 84 IOCAP PIE1 PIE2 OSFIE — C1IE
PIC12(L)F1840 10.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC12(L)F1840 10.1 Independent Clock Source 10.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. 10.2 Time-Out Period The WDTPS bits of the WDTCON register set the time-out period from 1ms to 256 seconds. After a Reset, the default time-out period is 2 seconds. WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word 1. See Table 10-1. 10.2.
PIC12(L)F1840 REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits
PIC12(L)F1840 NOTES: DS41441B-page 96 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 11.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL 11.1 The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs).
PIC12(L)F1840 11.2 11.2.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 30.
PIC12(L)F1840 Required Sequence EXAMPLE 11-2: DATA EEPROM WRITE BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BTFSC GOTO INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, $-2 ;Disable INTs.
PIC12(L)F1840 11.3 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash Program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software.
PIC12(L)F1840 EXAMPLE 11-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI: PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF BCF BSF NOP NOP BSF EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; ; Do not sel
PIC12(L)F1840 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH:EEADRL register pair with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD, FREE and WREN bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the erase operation.
PIC12(L)F1840 After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will FIGURE 11-2: continue to run. The processor does not stall when LWLO = 1, loading the write latches.
PIC12(L)F1840 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2.
PIC12(L)F1840 EXAMPLE 11-5: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. The 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC12(L)F1840 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. 8. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC12(L)F1840 11.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 11-6) to the desired value to be written. Example 11-6 shows how to verify a write to EEPROM.
PIC12(L)F1840 REGISTER 11-1: R/W-x/u EEDATL: EEPROM DATA REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM DATA
PIC12(L)F1840 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select
PIC12(L)F1840 REGISTER 11-6: W-0/0 EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit
PIC12(L)F1840 12.0 I/O PORTS 12.1 In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. The port has three registers for its operation. These registers are: • TRISA register (data direction register) • PORTA register (reads the levels on the pins of the device) • LATA register (output latch) Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins.
PIC12(L)F1840 REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RXDTSEL: Pin Selection bit 0 = RX/DT function is on RA1 1 = RX/DT
PIC12(L)F1840 12.2 PORTA Registers PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as ‘1’.
PIC12(L)F1840 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists.
PIC12(L)F1840 REGISTER 12-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1:
PIC12(L)F1840 REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented:
PIC12(L)F1840 REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits 1 = Pull-up enabled
PIC12(L)F1840 NOTES: DS41441B-page 118 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 13.0 INTERRUPT-ON-CHANGE 13.3 The PORTA pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTA pin, or combination of PORTA pins, can be configured to generate an interrupt.
PIC12(L)F1840 REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP<5:0>: Interrupt-on-Chang
PIC12(L)F1840 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 116 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 120 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 120 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 120 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 115 Name IOCAP —
PIC12(L)F1840 NOTES: DS41441B-page 122 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 14.0 FIXED VOLTAGE REFERENCE (FVR) 14.1 The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • • • • • Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, DAC and CPS module is routed through two independent programmable gain amplifiers.
PIC12(L)F1840 REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Refere
PIC12(L)F1840 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC12(L)F1840 NOTES: DS41441B-page 126 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 16.0 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC12(L)F1840 16.1 16.1.4 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.
PIC12(L)F1840 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 125 ns (2) (2) (2) (2) Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) Fosc/16 101 800 ns 800 ns 010 1.0 s Fosc/64 110 FRC x11 Fosc/32 Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.
PIC12(L)F1840 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC12(L)F1840 16.2 16.2.1 16.2.4 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 “A/D Conversion Procedure”.
PIC12(L)F1840 16.2.6 A/D CONVERSION PROCEDURE EXAMPLE 16-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC12(L)F1840 16.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC12(L)F1840 REGISTER 16-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified.
PIC12(L)F1840 REGISTER 16-3: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 16-4: R/W-x/u ADRES
PIC12(L)F1840 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC12(L)F1840 16.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4.
PIC12(L)F1840 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC12(L)F1840 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 133 ADCON1 ADFM ADCS2 ADCS1 ADCS0 — — ADPREF1 ADPREF0 134 ADRESH A/D Result Register High 135, 136 ADRESL A/D Result Register Low 135, 136 — — — ANSA4 — ANSA2 ANSA1 ANSA0 116 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 207 DACCON0 DACEN DACLPS DACOE — DA
PIC12(L)F1840 NOTES: DS41441B-page 140 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 17.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register.
PIC12(L)F1840 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD 5 VREF DACR<4:0> R R DACPSS<1:0> 2 R DACEN DACLPS R 32 Steps R 32-to-1 MUX R R DAC (To Comparator, CPS and ADC Modules) DACOUT R DACOE VSOURCE- VSS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS41441B-page 142 DACOUT Preliminary + – Buffered DAC Output 2011 Microchip Technology Inc.
PIC12(L)F1840 17.4 Low-Power Voltage State In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSOURCE+), or the negative voltage source, (VSOURCE-) can be disabled. The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source. 17.4.
PIC12(L)F1840 REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 DACEN DACLPS DACOE — R/W-0/0 R/W-0/0 DACPSS<1:0> U-0 R/W-0/0 — DACNSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 DACLPS: DAC Low
PIC12(L)F1840 18.0 SR LATCH The module consists of a single SR Latch with multiple Set and Reset inputs as well as separate latch outputs. The SR Latch module includes the following features: • • • • The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver. 18.3 Effects of a Reset Upon any device Reset, the SR Latch output is not initialized to a known state.
PIC12(L)F1840 FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRPS SRLEN SRQEN Pulse Gen(2) SRI S SRSPE Q SRCLK SRQ SRSCKE SYNCC1OUT(3) SRSC1E SR Latch(1) SRPR Pulse Gen(2) SRI R SRRPE Q SRNQ SRCLK SRRCKE SRLEN SYNCC1OUT(3) SRRC1E SRNQEN Note 1: 2: 3: DS41441B-page 146 If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 Pulse generator causes a 1 Q-state pulse width. Name denotes the connection point at the comparator output. Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 TABLE 18-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 110 256 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz 101 100 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz 011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz 010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz 001 8 4 MHz 2.
PIC12(L)F1840 REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE Reserved SRSC1E SRRPE SRRCKE Reserved SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SR Latch is set when th
PIC12(L)F1840 TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 147 SRCON1 SRSPE SRSCKE Reserved SRSC1E SRRPE SRRCKE Reserved SRRC1E 148 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 115 Name TRISA Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR Latch module. 2011 Microchip Technology Inc.
PIC12(L)F1840 NOTES: DS41441B-page 150 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 19.0 COMPARATOR MODULE FIGURE 19-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC12(L)F1840 FIGURE 19-2: COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM C1NCH C1ON(1) 2 C1INTP Interrupt det Set C1IF C1IN0- 0 (2) C1IN1- det 1 C1POL C1VN D C1(3) C1VP 0 MUX 1 (2) C1IN+ DAC FVR Buffer2 C1INTN Interrupt MUX C1OUT MC1OUT Q To Data Bus + EN Q1 C1HYS C1SP To ECCP PWM Logic 2 3 C1SYNC C1ON VSS C1PCH<1:0> 0 C1OE TRIS bit C1OUT 2 D (from Timer1) T1CLK Q 1 To Timer1 or SR Latch SYNCC1OUT Note 1: 2: 3: When C1ON = 0, the Comparator will produce a ‘0’ at the out
PIC12(L)F1840 19.2 19.2.3 Comparator Control The comparator has 2 control registers: CM1CON0 and CM1CON1. The CM1CON0 register (see Register 19-1) contains Control and Status bits for the following: • • • • • • Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs.
PIC12(L)F1840 19.3 Comparator Hysteresis 19.5 A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the C1HYS bit of the CM1CON0 register. Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. See Section 30.
PIC12(L)F1840 19.7 Comparator Negative Input Selection 19.10 Analog Input Connection Considerations The C1NCH bit of the CM1CON1 register directs one of two analog pins to the comparator inverting input. Note: 19.8 To use C1IN+ and C1INx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
PIC12(L)F1840 FIGURE 19-3: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS VA = Analog Voltage = Threshold Voltage VT Note 1: DS41441B-page 156 See Section 30.0 “Electrical Specifications”. Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 REGISTER 19-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator Enable bit 1 = Comparator is enabled and consumes no active power 0
PIC12(L)F1840 REGISTER 19-2: CM1CON1: COMPARATOR C1 CONTROL REGISTER 1 R/W-0/0 R/W-0/0 C1INTP C1INTN R/W-0/0 R/W-0/0 C1PCH<1:0> U-0 U-0 U-0 R/W-0/0 — — — C1NCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1INTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The C1IF interrupt flag will
PIC12(L)F1840 20.0 20.1.2 TIMER0 MODULE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal.
PIC12(L)F1840 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register.
PIC12(L)F1840 REGISTER 20-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
PIC12(L)F1840 NOTES: DS41441B-page 162 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 21.0 • • • • TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: Figure 21-1 is a block diagram of the Timer1 module.
PIC12(L)F1840 21.1 Timer1 Operation 21.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 21-2 displays the clock source selections. 21.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle.
PIC12(L)F1840 21.3 Timer1 Prescaler 21.6 Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable.
PIC12(L)F1840 21.6.2.1 T1G Pin Gate Operation 21.6.4 The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 Gate circuitry. 21.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 21.6.2.
PIC12(L)F1840 21.7 Timer1 Interrupt 21.9 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
PIC12(L)F1840 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41441B-page 168 N N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8 2011 Microchip Technology Inc.
PIC12(L)F1840 FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF N N+1 Set by hardware on falling edge of T1GVAL Cleared by software 2011 Microchip Technology Inc.
PIC12(L)F1840 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF DS41441B-page 170 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL Preliminary N+4 Cleared by software 2011 Microchip Technology Inc.
PIC12(L)F1840 21.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 21-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC12(L)F1840 21.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 21-2, is used to control Timer1 Gate.
PIC12(L)F1840 TABLE 21-5: Name ANSELA CCP1CON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 116 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 207 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 84 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 86 TMR1H Holding Register for the Most Significa
PIC12(L)F1840 NOTES: DS41441B-page 174 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 22.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP1 modules See Figure 22-1 for a block diagram of Timer2.
PIC12(L)F1840 22.1 Timer2 Operation 22.3 The clock input to the Timer2 modules is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle.
PIC12(L)F1840 REGISTER 22-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 T2OUTPS<3:0> R/W-0/0 R/W-0/0 TMR2ON bit 7 R/W-0/0 T2CKPS<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer Output Postscaler Select bits 0000 = 1:1 Postscaler
PIC12(L)F1840 TABLE 22-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 CCP1CON INTCON PIE1 Bit 6 P1M<1:0> Bit 5 Bit 4 Bit 3 DC1B<1:0> Bit 2 Bit 1 Bit 0 CCP1M<3:0> 207 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 84 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF PR2 Timer2 Module Period Register T2CON TMR2 Register on Page — 86 175* T2OUTPS<3:0> TMR2ON T2CKPS1 T2CKPS0 Holding Register for
PIC12(L)F1840 23.0 Using this method, the DSM can generate the following types of Key Modulation schemes: DATA SIGNAL MODULATOR The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output.
PIC12(L)F1840 23.1 DSM Operation 23.3 The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register, disables the DSM module by automatically switching the carrier high and carrier low signals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current.
PIC12(L)F1840 FIGURE 23-2: ON OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 EXAMPLE 23-1: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 CARH Active Carrier State FIGURE 23-3: CARL CARH CARL CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Car
PIC12(L)F1840 FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State FIGURE 23-5: CARH CARL CARH CARL FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Falling edges used to sync Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State DS41441B-page 182 CARH CARL Preliminary CARH CARL 2011 Microchip Technology Inc.
PIC12(L)F1840 23.5 Carrier Source Polarity Select 23.11 Operation in Sleep Mode The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL register. 23.
PIC12(L)F1840 REGISTER 23-1: MDCON: MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R-0/0 U-0 U-0 R/W-0/0 MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modu
PIC12(L)F1840 REGISTER 23-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-x/u U-0 U-0 U-0 MDMSODIS — — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDMS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDMSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by
PIC12(L)F1840 REGISTER 23-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 MDCHODIS MDCHPOL MDCHSYNC — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the p
PIC12(L)F1840 REGISTER 23-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 MDCLODIS MDCLPOL MDCLSYNC — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the per
PIC12(L)F1840 NOTES: DS41441B-page 188 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 24.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
PIC12(L)F1840 24.1 24.1.2 Capture Mode Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCP1 pin, the 16-bit CCPR1H:CCPR1L register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively.
PIC12(L)F1840 24.1.5 CAPTURE DURING SLEEP 24.1.6 Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON.
PIC12(L)F1840 24.2 24.2.2 Compare Mode Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPR1H:CCPR1L register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair.
PIC12(L)F1840 24.2.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section 12.1 “Alternate Pin Function” for more information.
PIC12(L)F1840 24.3 FIGURE 24-3: PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
PIC12(L)F1840 24.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP1 module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCP1 pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP1 module for the PWM mode by loading the CCP1CON register with the appropriate values. Load the CCPR1L register and the DC1B1 bits of the CCP1CON register, with the PWM duty cycle value.
PIC12(L)F1840 24.3.5 PWM RESOLUTION EQUATION 24-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 24-4.
PIC12(L)F1840 24.3.6 OPERATION IN SLEEP MODE 24.3.9 In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 24.3.7 CHANGES IN SYSTEM CLOCK FREQUENCY ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON.
PIC12(L)F1840 24.4 The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins is configurable and is selected by setting the bits CCP1M<3:0> in the CCP1CON register appropriately. PWM (Enhanced Mode) The enhanced PWM mode generates a Pulse-Width Modulation (PWM) signal on up to two different output pins with up to 10 bits of resolution.
PIC12(L)F1840 TABLE 24-8: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M<1:0> CCP1/P1A P1B Single 00 Yes(1) Yes(1) Half-Bridge 10 Yes Yes Note 1: PWM Steering enables outputs in Single mode.
PIC12(L)F1840 24.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 24-9). This mode can be used for Half-Bridge applications, as shown in Figure 24-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.
PIC12(L)F1840 24.4.2 ENHANCED PWM AUTOSHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the CCP1AS<2:0> bits of the CCP1AS register.
PIC12(L)F1840 24.4.3 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the P1RSEN bit in the PWM1CON register. If auto-restart is enabled, the CCP1ASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCP1ASE bit will be cleared via hardware and normal operation will resume.
PIC12(L)F1840 24.4.4 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 24-12: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC12(L)F1840 24.4.5 PWM STEERING MODE 24.4.5.1 In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCP1M<3:2> = 11 and P1M<1:0> = 00 of the CCP1CON register), the user firmware can bring out the same PWM signal to one or two output pins by setting the appropriate STR1 bits of the PSTR1CON register, as shown in Table 24-8.
PIC12(L)F1840 FIGURE 24-15: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STR1SYNC = 0) PWM Period PWM STR1 P1 PORT Data PORT Data P1n = PWM FIGURE 24-16: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STR1SYNC = 1) PWM STR1 P1 PORT Data PORT Data P1n = PWM 2011 Microchip Technology Inc.
PIC12(L)F1840 24.4.7 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section 12.1 “Alternate Pin Function” for more information.
PIC12(L)F1840 REGISTER 24-1: R/W-00 CCP1CON: CCP1 CONTROL REGISTER R/W-0/0 P1M<1:0> R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DC1B<1:0> R/W-0/0 R/W-0/0 CCP1M<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits Capture mode: Unused Compare mode: Unused PWM mode: If CCP1
PIC12(L)F1840 REGISTER 24-2: R/W-0/0 CCP1AS: CCP1 AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 CCP1ASE R/W-0/0 R/W-0/0 CCP1AS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 PSS1AC<1:0> R/W-0/0 PSS1BD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP1ASE: CCP1 Auto-Shutdown Event Status bit 1 = A shutdown event has occurred;
PIC12(L)F1840 REGISTER 24-3: R/W-0/0 PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 P1RSEN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 P1DC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCP1ASE bit clears automatically once the shutdown even
PIC12(L)F1840 NOTES: DS41441B-page 210 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 25.0 MASTER SYNCHRONOUS SERIAL PORT MODULE 25.1 Master SSP (MSSP1) Module Overview The Master Synchronous Serial Port (MSSP1) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC12(L)F1840 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 25-2 is a block diagram of the I2C interface module in Master mode.
PIC12(L)F1840 FIGURE 25-3: MSSP1 BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSP1BUF Reg SCL Shift Clock SSP1SR Reg SDA MSb LSb SSP1MSK Reg Match Detect Addr Match SSP1ADD Reg Start and Stop bit Detect 2011 Microchip Technology Inc.
PIC12(L)F1840 25.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select.
PIC12(L)F1840 FIGURE 25-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 25.2.1 SPI MODE REGISTERS The MSSP1 module has five registers for SPI mode operation.
PIC12(L)F1840 25.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSP1CON1<5:0> and SSP1STAT<7:6>).
PIC12(L)F1840 FIGURE 25-5: SPI MASTER/SLAVE CONNECTION SPI Master SSP1M<3:0> = 00xx = 1010 SPI Slave SSP1M<3:0> = 010x SDI SDO Serial Input Buffer (BUF) LSb SCK General I/O Processor 1 2011 Microchip Technology Inc.
PIC12(L)F1840 25.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 25-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSP1BUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC12(L)F1840 25.2.4 25.2.5 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSP1IF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSP1CON1 register.
PIC12(L)F1840 FIGURE 25-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 25-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Shift register SSP1SR and bit count are reset SSP1BUF to SSP1SR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF DS41441B-page 220 Prelim
PIC12(L)F1840 FIGURE 25-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active FIGURE 25-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
PIC12(L)F1840 25.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP1 clock is much faster than the system clock. In Slave mode, when MSSP1 interrupts are enabled, after the master completes sending data, an MSSP1 interrupt will wake the controller from Sleep.
PIC12(L)F1840 25.3 I2C MODE OVERVIEW FIGURE 25-11: The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 25-11 shows a typical connection between two processors configured as master and slave devices.
PIC12(L)F1840 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration.
PIC12(L)F1840 TABLE 25-2: TERM I2C BUS TERMS 25.4.5 Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus.
PIC12(L)F1840 FIGURE 25-12: I2C START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 25-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition DS41441B-page 226 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 25.4.9 ACKNOWLEDGE SEQUENCE 25.5 The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
PIC12(L)F1840 25.5.2 SLAVE RECEPTION 25.5.2.2 When the R/W bit of a matching received address byte is clear, the R/W bit of the SSP1STAT register is cleared. The received address is loaded into the SSP1BUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSP1STAT register is set, or bit SSP1OV of the SSP1CON1 register is set.
2011 Microchip Technology Inc. Preliminary SSP1OV BF SSP1IF S 1 A7 2 A6 3 A5 4 A4 5 A3 Receiving Address 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 5 D3 6 D2 7 D1 SSP1BUF is read Cleared by software 3 D4 Receiving Data D5 8 9 2 D6 First byte of data is available in SSP1BUF 1 D0 ACK D7 4 5 D3 6 D2 7 D1 8 D0 SSP1OV set because SSP1BUF is still full. ACK is not sent.
DS41441B-page 230 Preliminary CKP SSP1OV BF SSP1IF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSP1BUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSP1BUF 6 D2 7 D1 SSP1OV set because SSP1BUF is still full. ACK is not sent.
2011 Microchip Technology Inc.
DS41441B-page 232 Preliminary P S ACKTIM CKP ACKDT BF SSP1IF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSP1BUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of
PIC12(L)F1840 25.5.3 SLAVE TRANSMISSION 25.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSP1STAT register is set. The received address is loaded into the SSP1BUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission.
DS41441B-page 234 Preliminary P S D/A R/W ACKSTAT CKP BF SSP1IF S 1 2 5 6 7 8 Received address is read from SSP1BUF 4 Indicates an address has been received R/W is copied from the matching address byte When R/W is set SCL is always held low after 9th SCL falling edge 3 9 Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSP1BUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 M
PIC12(L)F1840 25.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSP1CON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSP1IF interrupt is set. Figure 25-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
DS41441B-page 236 Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSP1IF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSP1BUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC12(L)F1840 25.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 25.5.5 This section describes a standard sequence of events for the MSSP1 module configured as an I2C Slave in 10-bit Addressing mode. Figure 25-19 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle.
DS41441B-page 238 Preliminary CKP UA BF SSP1IF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low 9 ACK If address matches SSP1ADD it is loaded into SSP1BUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSP1ADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSP1BUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2
2011 Microchip Technology Inc.
DS41441B-page 240 Preliminary D/A R/W ACKSTAT CKP UA BF SSP1IF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSP1ADD must be updated SSP1BUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSP1ADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from t
PIC12(L)F1840 25.5.6 CLOCK STRETCHING 25.5.6.2 Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL.
PIC12(L)F1840 25.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC12(L)F1840 25.6 I2C MASTER MODE 25.6.1 Master mode is enabled by setting and clearing the appropriate SSP1M bits in the SSP1CON1 register and by setting the SSP1EN bit. In Master mode, the SCL and SDA lines are set as inputs and are manipulated by the MSSP1 hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP1 module is disabled.
PIC12(L)F1840 25.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD<7:0> and begins counting.
PIC12(L)F1840 25.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSP1CON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD<7:0> and starts its count.
PIC12(L)F1840 25.6.5 I2C MASTER MODE REPEATED SSP1CON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSP1STAT register will be set. The SSP1IF bit will not be set until the Baud Rate Generator has timed out.
PIC12(L)F1840 25.6.6 I2C MASTER MODE TRANSMISSION 25.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSP1BUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted.
DS41441B-page 248 S Preliminary R/W PEN SEN BF (SSP1STAT<0>) SSP1IF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSP1BUF written 1 D7 1 SCL held low while CPU responds to SSP1IF ACK = 0 R/W = 0 SSP1BUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSP1BUF is written by software Cleared by software service routine from SSP1 interrupt 2 D
PIC12(L)F1840 25.6.7 I2C MASTER MODE RECEPTION 25.6.7.4 Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSP1CON2 register. Note: The MSSP1 module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSP1SR.
DS41441B-page 250 Preliminary RCEN ACKEN SSP1OV BF (SSP1STAT<0>) SDA = 0, SCL = 1 while CPU responds to SSP1IF SSP1IF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSP1IF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA\ = ACKDT = 0 Clear
PIC12(L)F1840 25.6.8 ACKNOWLEDGE SEQUENCE TIMING 25.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSP1CON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC12(L)F1840 FIGURE 25-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSP1STAT<4>) is set. Write to SSP1CON2, set PEN PEN bit (SSP1CON2<2>) is cleared by hardware and the SSP1IF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 25.6.10 SLEEP OPERATION 25.6.
PIC12(L)F1840 FIGURE 25-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF 2011 Microchip Technology Inc.
PIC12(L)F1840 25.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 25-32). SCL is sampled low before SDA is asserted low (Figure 25-33). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 25-34).
PIC12(L)F1840 FIGURE 25-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF.
PIC12(L)F1840 25.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 25-35). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC12(L)F1840 25.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSP1ADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 25-37).
PIC12(L)F1840 TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 84 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF PIR2 OSFIF — C1IF EEIF BCL1IF — — — 87 SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 264 Name INTCON
PIC12(L)F1840 25.7 BAUD RATE GENERATOR The MSSP1 module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSP1ADD register (Register 25-6). When a write occurs to SSP1BUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line.
PIC12(L)F1840 REGISTER 25-1: SSP1STAT: SSP1 STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampl
PIC12(L)F1840 REGISTER 25-2: SSP1CON1: SSP1 CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSP1OV SSP1EN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSP1M<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode:
PIC12(L)F1840 REGISTER 25-3: SSP1CON2: SSP1 CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in
PIC12(L)F1840 REGISTER 25-4: SSP1CON3: SSP1 CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in
PIC12(L)F1840 REGISTER 25-5: R/W-1/1 SSP1MSK: SSP1 MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSP1ADD to detect I2C address match 0 = The received address bit
PIC12(L)F1840 NOTES: 2011 Microchip Technology Inc.
PIC12(L)F1840 DS41441B-page 266 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 26.
PIC12(L)F1840 FIGURE 26-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC SPBRGH SPBRGL x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) ••• 7 1 LSb 0 START RX9 ÷n BRG16 Multiplier Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Re
PIC12(L)F1840 26.1 26.1.1.2 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC12(L)F1840 26.1.1.4 TSR Status 26.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 26.1.1.5 1. 2. 3.
PIC12(L)F1840 TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 278 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 84 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 86 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 277 Name BAUDCON INTCON RCSTA SPBRGL BRG<7:0> 279*
PIC12(L)F1840 26.1.2 EUSART ASYNCHRONOUS RECEIVER 26.1.2.2 The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 26-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC12(L)F1840 26.1.2.4 Receive Framing Error 26.1.2.7 Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC12(L)F1840 26.1.2.8 Asynchronous Reception Set-up: 26.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 26.3 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5.
PIC12(L)F1840 TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 278 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 84 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 86 SPEN RX9 SREN OERR RX9D Name BAUDCON INTCON RCREG RCSTA EUSART Receive Data Register SPBRGL ADDEN
PIC12(L)F1840 26.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 26-1: The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output.
PIC12(L)F1840 RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) REGISTER 26-2: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pin
PIC12(L)F1840 REGISTER 26-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud
PIC12(L)F1840 26.3 EXAMPLE 26-1: EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode.
PIC12(L)F1840 TABLE 26-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: FOSC/[4 (n+1)] x = Don’t care, n = value of SPBRGH, SPBRGL register pair.
PIC12(L)F1840 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.
PIC12(L)F1840 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC12(L)F1840 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.
PIC12(L)F1840 26.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC12(L)F1840 26.3.2 AUTO-BAUD OVERFLOW 26.3.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC12(L)F1840 FIGURE 26-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC12(L)F1840 26.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC12(L)F1840 26.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC12(L)F1840 FIGURE 26-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
PIC12(L)F1840 26.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC12(L)F1840 FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC12(L)F1840 26.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC12(L)F1840 26.4.2.3 EUSART Synchronous Slave Reception 26.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 26.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC12(L)F1840 26.5 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 26.5.
PIC12(L)F1840 27.0 CAPACITIVE SENSING (CPS) MODULE The Capacitive Sensing (CPS) module allows for an interaction with an end user without a mechanical interface. In a typical application, the CPS is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the CPS module.
PIC12(L)F1840 FIGURE 27-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM Oscillator Module VDD (1) + (2) - S CPSx (1) Analog Pin - Q CPSCLK R (2) + Internal References Ref- 0 0 Ref+ 1 DAC 1 FVR CPSRM Note 1: 2: Module Enable and Power mode selections are not shown. Comparator remains active in Noise Detection mode. DS41441B-page 296 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 27.1 Analog MUX 27.3 The CPS can monitor up to four inputs. See Register 27-2 for details. The capacitive sensing inputs are defined as CPS<7:0>, as applicable to device. To determine if a frequency change has occurred the user must: • Select the appropriate CPS pin by setting the appropriate CPSCH bits of the CPSCON1 register. • Set the corresponding ANSEL bit. • Set the corresponding TRIS bit. • Run the software algorithm.
PIC12(L)F1840 27.4 The remaining mode is a Noise Detection mode that resides within the high range. The Noise Detection mode is unique in that it disables the sinking and sourcing of current on the analog pin but leaves the rest of the oscillator circuitry active. This reduces the oscillation frequency on the analog pin to zero and also greatly reduces the current consumed by the oscillator module. Power Modes The capacitive sensing oscillator can operate in one of seven different power modes.
PIC12(L)F1840 27.5 Timer Resources 27.7 To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer, divided by the period of the fixed time base. 27.
PIC12(L)F1840 27.7.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed information on the software required for CPS module.
PIC12(L)F1840 REGISTER 27-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 U-0 CPSON CPSRM — — R/W-0/0 R/W-0/0 CPSRNG<1:0> R-0/0 R/W-0/0 CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSON: CPS Module Enable bit 1 = CPS module is enabled 0 = CPS module is disabled bit
PIC12(L)F1840 REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0/0 R/W-0/0 CPSCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 CPSCH<1:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are
PIC12(L)F1840 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications.
PIC12(L)F1840 28.2 FIGURE 28-2: Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC12F/LF1840 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. VDD Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2.
PIC12(L)F1840 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 28-4 for more information.
PIC12(L)F1840 NOTES: DS41441B-page 306 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC12(L)F1840 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k
PIC12(L)F1840 TABLE 29-3: PIC12F/LF1840 ENHANCED INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear
PIC12(L)F1840 TABLE 29-3: PIC12F/LF1840 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG re
PIC12(L)F1840 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: (W) .AND. (k) (W) Operation: FSR(n) + k FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.
PIC12(L)F1840 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC12(L)F1840 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC12(L)F1840 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC12(L)F1840 LSLF Logical Left Shift MOVF Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC12(L)F1840 MOVIW Move INDFn to W MOVLP Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Syntax: [ label ] MOVLP k Operands: 0 k 127 Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements)
PIC12(L)F1840 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Syntax: [ label ] Operands: None n [0,1] mm [00,01, 10, 11] -32 k 31 Description: No operation.
PIC12(L)F1840 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] None RETFIE RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC12(L)F1840 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC12(L)F1840 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC12(L)F1840 30.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC12F1840 ............................................................................. -0.
PIC12(L)F1840 PIC12F1840 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 30-1: VDD (V) 5.5 2.5 2.3 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies. PIC12LF1840 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 30-2: 3.6 2.5 1.
PIC12(L)F1840 FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 25 ± 2% 0 -20 -40 1.8 ± 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2011 Microchip Technology Inc.
PIC12(L)F1840 30.1 DC Characteristics: PIC12(L)F1840-I/E (Industrial, Extended) PIC12LF1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD D001 D002* VDR D002* Characteristic Min. Typ† Max.
PIC12(L)F1840 FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2011 Microchip Technology Inc.
PIC12(L)F1840 30.2 DC Characteristics: PIC12(L)F1840-I/E (Industrial, Extended) PIC12LF1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max. Units VDD Note Supply Current (IDD)(1, 2) — 5.
PIC12(L)F1840 30.2 DC Characteristics: PIC12(L)F1840-I/E (Industrial, Extended) (Continued) PIC12LF1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Conditions Device Characteristics Min. Typ† Max. Units VDD — 172 300 A 2.
PIC12(L)F1840 30.2 DC Characteristics: PIC12(L)F1840-I/E (Industrial, Extended) (Continued) PIC12LF1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC12(L)F1840 30.3 DC Characteristics: PIC12(L)F1840-I/E (Power-Down) PIC12LF1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Power-down Base Current Min. Typ† Conditions Max. +85°C Max.
PIC12(L)F1840 30.3 DC Characteristics: PIC12(L)F1840-I/E (Power-Down) (Continued) PIC12LF1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Power-down Base Current (IPD) D026A* D026A* Typ† Conditions Max.
PIC12(L)F1840 30.3 DC Characteristics: PIC12(L)F1840-I/E (Power-Down) (Continued) PIC12LF1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC12F1840 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Typ† Max. +85°C Max.
PIC12(L)F1840 30.4 DC Characteristics: PIC12(L)F1840-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units — — with Schmitt Trigger buffer with I2C™ levels Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.0V VDD 5.5V — — 0.
PIC12(L)F1840 30.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Voltage on MCLR/VPP/RA5 pin 8.0 — 9.0 V VDD for Bulk Erase 2.7 — VDD max. V Conditions Program Memory Programming Specifications D110 VIHH D112 D113 VPEW VDD for Write or Row Erase VDD min. — VDD max.
PIC12(L)F1840 30.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic Typ.
PIC12(L)F1840 30.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC12(L)F1840 30.8 AC Characteristics: PIC12F/LF1840-I/E FIGURE 30-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym.
PIC12(L)F1840 TABLE 30-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS08 Sym. HFOSC OS08A MFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2) Internal Calibrated MFINTOSC Frequency(2) Internal LFINTOSC Frequency OS09 LFOSC OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time MFINTOSC Wake-up from Sleep Start-up Time Freq. Tolerance Min. Typ† Max. Units Conditions 2% — 16.
PIC12(L)F1840 FIGURE 30-7: Cycle CLKOUT AND I/O TIMING Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS16 OS13 OS18 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 DS41441B-page 338 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions — — 70 ns VDD = 3.0-5.0V — — 72 ns VDD = 3.0-5.
PIC12(L)F1840 FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’. 2 ms delay if PWRTE = 0 and VREGEN = 1. DS41441B-page 340 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 31 TWDTLP Watchdog Timer Time-out Period 10 16 27 ms VDD = 3.
PIC12(L)F1840 FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min.
PIC12(L)F1840 FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 30-5 for load conditions. TABLE 30-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. No. Characteristic CC01* TccL CCP Input Low Time CC02* TccH CCP Input High Time CC03* TccP * † Min. Typ† Max. Units 0.5TCY + 20 — — ns With Prescaler 20 — — ns No Prescaler 0.
PIC12(L)F1840 TABLE 30-9: PIC12(L)F1840 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym. Characteristic AD130* TAD AD131 TCNV AD132* TACQ Min. Typ† Max. Units Conditions A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal RC Oscillator Period 1.0 1.6 6.
PIC12(L)F1840 FIGURE 30-13: PIC12(L)F1840 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 Sampling Stopped Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2011 Microchip Technology Inc.
PIC12(L)F1840 TABLE 30-10: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym. Characteristics Min. Typ. Max. Units — ±7.
PIC12(L)F1840 TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. Max. Units — 80 ns US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time (Master mode) 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.
PIC12(L)F1840 FIGURE 30-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDOx LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions.
PIC12(L)F1840 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE = 0) SSx SP70 SCKx (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 MSb SDOx LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions.
PIC12(L)F1840 TABLE 30-14: SPI MODE REQUIREMENTS Param No. Symbol Characteristic Min. Typ† Max.
PIC12(L)F1840 FIGURE 30-21: I2C™ BUS DATA TIMING SP103 SCLx SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDAx In SP92 SP110 SP109 SP109 SDAx Out Note: Refer to Figure 30-5 for load conditions. 2011 Microchip Technology Inc.
PIC12(L)F1840 TABLE 30-15: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH SP101* TLOW SP102* TR SP103* TF SP106* THD:DAT SP107* TSU:DAT SP109* TAA SP110* SP111 * Note 1: 2: TBUF CB Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSPx module 1.5TCY — — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.
PIC12(L)F1840 TABLE 30-16: CAP SENSE OSCILLATOR SPECIFICATIONS Param. No. CS01 CS02 Symbol ISRC ISNK Characteristic Current Source Current Sink CS03 VCTH Cap Threshold CS04 VCTL Cap Threshold CS05 VCHYST CAP HYSTERESIS (VCTH - VCTL) Min. Typ† Max. Units High -1.25 -8 -15 A Medium -0.8 -1.5 -3 A Low -0.1 -0.3 -0.6 A High 1.25 7.5 14 A Medium 0.6 1.5 3.2 A Low 0.1 0.25 1.5 A — 0.8 — mV — 0.
PIC12(L)F1840 NOTES: DS41441B-page 354 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. 2011 Microchip Technology Inc.
PIC12(L)F1840 NOTES: DS41441B-page 356 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 32.0 DEVELOPMENT SUPPORT 32.
PIC12(L)F1840 32.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 32.
PIC12(L)F1840 32.7 MPLAB SIM Software Simulator 32.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC12(L)F1840 32.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 32.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC12(L)F1840 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 8-Lead PDIP (300 mil) Example 12F1840 /P017 XXXXXXXX XXXXXNNN 1012 YYWW 8-Lead SOIC (3.90 mm) Example 12F1840 /SN1012 017 NNN 8-Lead DFN (3x3x0.9 mm) Example XXXX YYWW NNN MFQ0 1012 017 PIN 1 PIN 1 Legend: XX...
PIC12(L)F1840 TABLE 33-1: 8-LEAD 3X3 DFN (MF) TOP MARKING Part Number Marking PIC12F1840-E/MF MFQ0 PIC12F1840(T)-I/MF MFR0 PIC12LF1840-E/MF MFS0 PIC12LF1840(T)-I/MF MFT0 DS41441B-page 362 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 33.2 Package Details The following sections give the technical details of the packages. 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6 &! ' ! 9 ' &! 7"') % ! 7,8.
PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41441B-page 364 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC12(L)F1840 ! "" #$ %& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS41441B-page 366 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41441B-page 368 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC12(L)F1840 NOTES: DS41441B-page 370 Preliminary 2011 Microchip Technology Inc.
PIC12(L)F1840 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (02/2011) APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This section provides comparisons when migrating from other similar PIC® devices to the PIC12(L)F1840 family of devices. Original release of this data sheet. Revision B (05/2011) Updated ‘Special Microcontroller Features’ and ‘Low-Power Features’ sections; Updated Section 30.3, ‘DC Characteristics: PIC12(L)F1840-I/E (Power-down)’; Updated the Packaging Information section. B.
PIC12(L)F1840 Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device.
PIC12(L)F1840 INDEX A A/D Specifications.................................................... 343, 344 Absolute Maximum Ratings .............................................. 321 AC Characteristics Industrial and Extended ............................................ 336 Load Conditions ........................................................ 335 ACKSTAT ......................................................................... 247 ACKSTAT Status Flag ......................................................
PIC12(L)F1840 CCPR1L Register................................................................ 29 CCPxCON (ECCPx) Register ........................................... 207 CLKRCON Register ............................................................ 66 Clock Accuracy with Asynchronous Operation ................. 276 Clock Sources External Modes ........................................................... 49 EC ....................................................................... 49 HS .......................
PIC12(L)F1840 Associated Registers Receive..................................................... 293 Transmit.................................................... 292 Reception.......................................................... 293 Transmission .................................................... 292 Extended Instruction Set ADDFSR ................................................................... 311 F Fail-Safe Clock Monitor.......................................................
PIC12(L)F1840 Program ...................................................................... 15 Microchip Internet Web Site .............................................. 379 Migrating from other PIC Microcontroller Devices............. 371 MOVIW.............................................................................. 316 MOVLB.............................................................................. 316 MOVWI..............................................................................
PIC12(L)F1840 MDCARH (Modulation High Carrier Control Register) ........................................................... 186 MDCARL (Modulation Low Carrier Control Register) 187 MDCON (Modulation Control Register) .................... 184 MDSRC (Modulation Source Control Register) ........ 185 OPTION_REG (OPTION) ......................................... 161 OSCCON (Oscillator Control) ..................................... 61 OSCSTAT (Oscillator Status) .....................................
PIC12(L)F1840 Baud Rate Generator with Clock Arbitration ............. 244 BRG Reset Due to SDA Arbitration During Start Condition........................................................... 255 Brown-out Reset (BOR) ............................................ 340 Brown-out Reset Situations ........................................ 71 Bus Collision During a Repeated Start Condition (Case 1) ............................................................
PIC12(L)F1840 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC12(L)F1840 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
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