Datasheet

PIC12(L)F1822/16(L)F1823
DS40001413E-page 250  2010-2015 Microchip Technology Inc.
25.6.5 I
2
C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition (Figure 25-27) occurs when
the RSEN bit of the SSP1CON2 register is pro-
grammed high and the Master state machine is no lon-
ger active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the
Baud Rate Generator is loaded and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (T
BRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
and begins counting. SDA and SCL must be sampled
high for one T
BRG. This action is then followed by
assertion of the SDA pin (SDA = 0) for one T
BRG while
SCL is high. SCL is asserted low. Following this, the
RSEN bit of the SSP1CON2 register will be automati-
cally cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit of the SSP1STAT register will be set. The
SSP1IF bit will not be set until the Baud Rate Generator
has timed out.
FIGURE 25-27: REPEAT START CONDITION WAVEFORM
25.6.6 I
2
C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSP1BUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (T
BRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for T
BRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK
bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK
is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSP1IF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSP1BUF, leaving SCL low and SDA
unchanged (Figure 25-28).
After the write to the SSP1BUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W
bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK
bit is
loaded into the ACKSTAT Status bit of the SSP1CON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSP1IF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSP1BUF takes place,
holding SCL low and allowing SDA to float.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL
goes from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting to
transmit a data ‘1’.
SDA
SCL
Repeated Start
Write to SSP1CON2
Write to SSP1BUF occurs here
At completion of Start bit,
hardware clears RSEN bit
1st bit
S bit set by hardware
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change)
SCL = 1
occurs here
TBRG TBRG
TBRG
and sets SSP1IF
Sr