Datasheet

 2011-2015 Microchip Technology Inc. DS40001615C-page 69
PIC12(L)F1501
REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 U-0 U-0
— —C1IF— — NCO1IF — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5 C1IF: Comparator C1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4-3 Unimplemented: Read as ‘0’
bit 2 NCO1IF: Numerically Controlled Oscillator Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 1-0 Unimplemented: Read as ‘0’
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.