Datasheet

 2011-2015 Microchip Technology Inc. DS40001615C-page 227
PIC12(L)F1501
FIGURE 27-11: CLC PROPAGATION TIMING
TABLE 27-12: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym. Characteristic Min. Typ† Max. Units Conditions
CLC01* T
CLCIN CLC input time — 7 — ns
CLC02* TCLC CLC module input to output propagation time —
—
24
12
—
—
ns
ns
VDD = 1.8V
V
DD > 3.6V
CLC03* T
CLCOUT CLC output time Rise Time — OS18 — — (Note 1)
Fall Time — OS19 — — (Note 1)
CLC04* FCLCMAX CLC maximum switching frequency — 45 — MHz
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note1:See Table 27-9 for OS18 and OS19 rise and fall times.
LCx_in[n]
(1)
CLC
Output time
CLC
Input time
LCx_out
(1)
CLCx
CLCxINn
CLC
Module
CLC01 CLC02 CLC03
LCx_in[n]
(1)
CLC
Output time
CLC
Input time
LCx_out
(1)
CLCx
CLCxINn
CLC
Module
Rev. 10-000031A
7/30/2013
Note 1: See FIGURE 22-1:, Configurable Logic Cell Block Diagram, to identify specific CLC signals.