PIC12(L)F1501 8-Pin Flash, 8-Bit Microcontrollers High-Performance RISC CPU: • C Compiler Optimized Architecture • Only 49 Instructions • Operating Speed: - DC – 20 MHz clock input - DC – 200 ns instruction cycle • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset • Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory Flexible Oscillator Structure: • 16 MH
PIC12(L)F1501 - True linear frequency control - High-speed clock input - Selectable Output modes - Fixed Duty Cycle (FDC) mode - Pulse Frequency (PF) mode • Complementary Waveform Generator (CWG): - Eight selectable signal sources - Selectable falling and rising edge dead-band control - Polarity control - Four auto-shutdown sources - Multiple input sources: PWM, CLC, NCO Peripheral Features (Continued): • Two Configurable Logic Cell (CLC) modules: - 16 selectable input source signals - Four inputs per modu
PIC12(L)F1501 PIN DIAGRAMS VDD 1 RA5 2 RA4 3 MCLR/VPP/RA3 4 PIC12(L)F1501 8-pin PDIP, SOIC, MSOP, DFN, UDFN 8 VSS 7 RA0/ICSPDAT 6 RA1/ICSPCLK 5 RA2 Note: See Table 1 for location of all peripheral functions. 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 PIN ALLOCATION TABLE AN1 VREF+ C1IN0- 5 AN2 DACOUT2 C1OUT RA3 4 — — — RA4 3 AN3 — C1IN1- RA5 2 — — — — — — NCO1 T0CKI CWG1A CWG1FLT — T1G(1) — — T1G CWG1B(1) T1CKI CWG1A(1) NCO1(1) NCO1CLK Basic 6 RA2 CWG1B Pull-Up RA1 — Interrupt C1IN+ PWM DACOUT1 CLC Comparator AN0 NCO Reference 7 CWG ADC RA0 Timer 8-Pin PDIP/SOIC/MSOP/DFN/UDFN 8-PIN ALLOCATION TABLE (PIC12(L)F1501) I/O TABLE 1: CLC2IN1 PWM2 IOC Y ICSPDAT CLC2IN0 — IOC Y
PIC12(L)F1501 TABLE OF CONTENTS 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 11 3.0 Memory Organization ................................................................................
PIC12(L)F1501 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC12(L)F1501 1.0 DEVICE OVERVIEW The block diagram of these devices are shown in Figure 1-1, the available peripherals are shown in Table 1-1, and the pinout descriptions are shown in Table 1-2.
PIC12(L)F1501 FIGURE 1-1: PIC12(L)F1501 BLOCK DIAGRAM Rev. 10-000039C 12/16/2013 Program Flash Memory RAM PORTA CLKOUT Timing Generation CPU CLKIN INTRC Oscillator (Note 3) MCLR TMR2 CWG1 NCO1 Note 1: 2: 3: DS40001615C-page 8 TMR1 TMR0 CLC2 C1 CLC1 Temp Indicator PWM4 ADC 10-bit PWM3 DAC PWM2 FVR PWM1 See applicable chapters for more information on peripherals. See Table 1-1 for peripherals on specific devices. See Figure 2-1. 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 TABLE 1-2: PIC12(L)F1501 PINOUT DESCRIPTION Name RA0/AN0/C1IN+/DACOUT1/ CWG1B(1)/CLC2IN1/PWM2/ ICSPDAT RA1/AN1/VREF+/C1IN0-/ NCO1(1)/CLC2IN0/ICSPCLK RA2/AN2/C1OUT/DACOUT2/ T0CKI/INT/PWM1/CLC1(1)/ CWG1A(1)/CWG1FLT RA3/CLC1IN0/VPP/T1G(1)/MCLR RA4/AN3/C1IN1-/CWG1B(1)/ CLC1(1)/PWM3/CLKOUT/T1G(1) Function Input Type Output Type RA0 TTL AN0 AN — A/D Channel input. C1IN+ AN — Comparator positive input. DACOUT1 — AN Digital-to-Analog Converter output.
PIC12(L)F1501 TABLE 1-2: PIC12(L)F1501 PINOUT DESCRIPTION (CONTINUED) Name RA5/CLKIN/T1CKI/CWG1A(1)/ NCO1(1)/NCO1CLK/CLC1IN1/ CLC2/PWM4 Function Input Type RA5 TTL CLKIN CMOS T1CKI ST CWG1A — Output Type Description CMOS General purpose I/O. — External clock input (EC mode). — Timer1 clock input. CMOS CWG complementary output. NCO1 ST — Numerically Controlled Oscillator output. NCO1CLK ST — Numerically Controlled Oscillator Clock source input.
PIC12(L)F1501 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC12(L)F1501 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep.
PIC12(L)F1501 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.
PIC12(L)F1501 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC12(L)F1501 Rev. 10-000040D 7/30/2013 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 3.2.1 There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.2.1.1 15 READING PROGRAM MEMORY AS DATA RETLW Instruction The RETLW instruction can be used to provide access to tables of constants.
PIC12(L)F1501 3.2.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
PIC12(L)F1501 3.3 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’.
PIC12(L)F1501 3.3.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC12(L)F1501 3.3.2 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.3.
2011-2015 Microchip Technology Inc. 3.3.5 DEVICE MEMORY MAPS The memory maps for Bank 0 through Bank 31 are shown in the tables in this section.
PIC12(L)F1501 MEMORY MAP (CONTINUED) BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 400h Status 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h Core Registers (Table 3-2) 480h Core Registers (Table 3-2) 500h Core Registers (Table 3-2) 580h Core Registers (Table 3-2) 600h Core Registers (Table 3-2) 680h Core Registers (Table 3-2) 700h Core Registers (Table 3-2) 780h Core Registers (Table 3-2) — — — — — — —
2011-2015 Microchip Technology Inc.
PIC12(L)F1501 TABLE 3-3: PIC12(L)F1501 MEMORY MAP (CONTINUED) Bank 31 Bank 30 F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F6Fh Legend: DS40001615C-page 22 — — — CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 F8Ch Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_S
PIC12(L)F1501 3.3.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-4 can be addressed from any Bank.
PIC12(L)F1501 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY Name Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx Bank 0 00Ch 00Dh to 010h PORTA — Unimplemented — — 011h PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 00-- --00 00-- --00 012h PIR2 — — C1IF — — NCO1IF — — --0- -0-- --0- -0-- 013h PIR3 — — — — — — CLC2IF CLC1IF ---- --00 ---- --00 014h — Unimp
PIC12(L)F1501 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — LATA5 LATA4 — LATA2 LATA1 LATA0 Value on POR, BOR Value on all other Resets Bank 2 10Ch 10Dh to 110h 111h 112h to 114h LATA — CM1CON0 — Unimplemented C1ON --xx -xxx --uu -uuu — C1OUT C1OE C1POL — C1SP C1HYS C1SYNC Unimplemented — 0000 -100 0000 -100 — — 115h CMOUT — — — — — — — MC1OUT ---- --00 ---- --00 116h BORCON SBOREN B
PIC12(L)F1501 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 Value on POR, BOR Value on all other Resets Bank 4 20Ch 20Dh to 21Fh WPUA --11 1111 --11 1111 — Unimplemented — — — Unimplemented — — — Unimplemented — — — Unimplemented — — Bank 5 28Ch to 29Fh Bank 6 30Ch to 31Fh Bank 7 38Ch to 390h 391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP
PIC12(L)F1501 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Unimplemented — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 10 50Ch to 51Fh — Bank 11 58Ch to 59Fh — Bank 12 60Ch to 610h — 611h PWM1DCL 612h PWM1DCH 613h PWM1CON0 614h PWM2DCL 615h PWM2DCH 616h PWM2CON0 617h PWM3DCL 618h PWM3DCH 619h PWM3CON0 61Ah PWM4DCL 61Bh PWM4DCH 61Ch PWM4CON0 6
PIC12(L)F1501 TABLE 3-5: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Banks 14-29 x0Ch/ x8Ch — x1Fh/ x9Fh — Bank 30 F0Ch to F0Eh — F0Fh CLCDATA — — — — — F10h CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN F11h CLC1POL LC1POL — — — F12h CLC1SEL0 — LC1D2S<2:0> — LC1D1S<2:0> F13h CLC1SEL1 — LC1D4S<2:0> — LC1D3S<2:0> F14h
PIC12(L)F1501 TABLE 3-5: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 31 F8Ch — FE3h — FE4h STATUS_ Unimplemented — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register Shad
PIC12(L)F1501 3.4 3.4.2 PCL and PCLATH The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC. FIGURE 3-3: LOADING OF PC IN DIFFERENT SITUATIONS Rev.
PIC12(L)F1501 3.5 3.5.1 Stack All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-4 through 3-7). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
PIC12(L)F1501 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 Rev. 10-000043B 7/30/2013 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-6: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 Rev.
PIC12(L)F1501 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 Rev. 10-000043D 7/30/2013 TOSH:TOSL 3.5.
PIC12(L)F1501 FIGURE 3-8: INDIRECT ADDRESSING Rev. 10-000044A 7/30/2013 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x0FFF Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved FSR Address Range 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001615C-page 34 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Rev.
PIC12(L)F1501 3.6.2 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC12(L)F1501 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers.
PIC12(L)F1501 4.
PIC12(L)F1501 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 (1) LVP U-1 — R/P-1 R/P-1 R/P-1 U-1 LPBOR BORV(2) STVREN — bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MC
PIC12(L)F1501 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
PIC12(L)F1501 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.
PIC12(L)F1501 5.0 OSCILLATOR MODULE The oscillator module can be configured in one of the following clock modes. 5.1 Overview 1. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module.
PIC12(L)F1501 FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM Rev. 10-000030C 7/30/2013 Sleep (2) EC CLKIN FOSC(1) to CPU and Peripherals INTOSC IRCF<3:0> HFINTOSC 16 MHz Start-up Control Logic 4 8 MHz 4 MHz 16 MHz Oscillator (1) HFINTOSC Fast Start-up Oscillator Prescaler 2 MHz Clock Control 1 MHz *500 kHz 3 *250 kHz FOSC<2:0> 2 SCS<1:0> *125 kHz 62.5 kHz *31.
PIC12(L)F1501 5.2 Clock Source Types FIGURE 5-2: EXTERNAL CLOCK (EC) MODE OPERATION Clock sources can be classified as external, internal or peripheral. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL modes). Internal clock sources are contained within the oscillator module.
PIC12(L)F1501 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<1:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 “Clock Switching”for more information.
PIC12(L)F1501 5.2.2.4 Peripheral Clock Sources 5.2.2.5 The clock sources described in this chapter and the Timer’s are available to different peripherals. Table 5-1 lists the clocks and timers available for each peripheral. ● ● TMR2 CLC TMR1 ● TMR0 ● LFINTOSC ADC HFINTOSC FRC PERIPHERAL CLOCK SOURCES FOSC TABLE 5-1: ● ● ● ● ● COMP The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register.
PIC12(L)F1501 FIGURE 5-3: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (WDT disabled) HFINTOSC Oscillator Delay(1) 2-cycle Sync Running 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock LFINTOSC (WDT enabled) HFINTOSC HFINTOSC LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT is enabled(2) LFINTOSC Oscillator Delay(1) 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock Note 1: 2: See Table 5-2, “Oscillator Switch
PIC12(L)F1501 5.3 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: • Default system oscillator determined by FOSC bits in Configuration Words • Internal Oscillator Block (INTOSC) 5.3.
PIC12(L)F1501 5.
PIC12(L)F1501 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER U-0 U-0 U-0 R-0/q U-0 U-0 R-0/q R-0/q — — — HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7-5 Unimplemented: Read as ‘0’ bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is
PIC12(L)F1501 6.0 RESETS There are multiple ways to reset this device: • • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-chip Reset Circuit is shown in Figure 6-1.
PIC12(L)F1501 6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC12(L)F1501 FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 6.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC12(L)F1501 6.4 Low-Power Brown-Out Reset (LPBOR) The Low-Power Brown-out Reset (LPBOR) operates like the BOR to detect low voltage conditions on the VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The BOR bit in PCON is used for both BOR and the LPBOR. Refer to Register 6-2.
PIC12(L)F1501 FIGURE 6-3: RESET START-UP SEQUENCE Rev. 10-000032B 7/30/2013 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Int. Oscillator FOSC Begin Execution code execution (1) Internal Oscillator, PWRTEN = 0 code execution (1) Internal Oscillator, PWRTEN = 1 VDD Internal POR TPWRT Power-up Timer MCLR Internal RESET Ext.
PIC12(L)F1501 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers.
PIC12(L)F1501 6.13 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 6-2. 6.
PIC12(L)F1501 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 53 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 57 STATUS — — — TO PD Z DC WDTCON — — WDTPS<4:0> C 17 SWDTEN 77 Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
PIC12(L)F1501 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details.
PIC12(L)F1501 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1, PIE2 and PIE3 registers) 7.
PIC12(L)F1501 FIGURE 7-2: INTERRUPT LATENCY Fosc Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1-Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Ins
PIC12(L)F1501 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC CLKOUT (3) INT pin (1) (1) INTF Interrupt Latency (2) (4) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h 0005h Inst (0004h) Inst (0005h) Forced NOP Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY.
PIC12(L)F1501 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC12(L)F1501 7.
PIC12(L)F1501 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 TMR1GIE ADIE — — — — TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disa
PIC12(L)F1501 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 U-0 U-0 — — C1IE — — NCO1IE — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0
PIC12(L)F1501 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — CLC2IE CLC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 CLC2IE: Configurable Logic Block 2 Interrupt Enable bit 1 = Enables the CLC 2 in
PIC12(L)F1501 REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 TMR1GIF ADIF — — — — TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit
PIC12(L)F1501 REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 U-0 U-0 R/W-0/0 U-0 U-0 R/W-0/0 U-0 U-0 — — C1IF — — NCO1IF — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is
PIC12(L)F1501 REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — CLC2IF CLC1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 CLC2IF: Configurable Logic Block 2 Interrupt Flag bit 1 = Interrupt is pending
PIC12(L)F1501 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 64 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA ADIE — — — — TMR2IE TMR1IE 65 — — C1IE — — NCO1IE — — 66 PIE3 — — — — — — CLC2IE CLC1IE 67 PIR1 TMR1GIF ADIF — — — — TMR2IF TMR1IF 68 PIR2 — — C1IF — — NCO1IF — — 68 PIR3 — — — — — — CLC2IF CLC1I
PIC12(L)F1501 8.0 POWER-DOWN MODE (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: 1. WDT will be cleared but keeps running, if enabled for operation during Sleep. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. 6.
PIC12(L)F1501 FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) TOST(3) CLKOUT(2) Interrupt flag Interrupt Latency (4) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 8.
PIC12(L)F1501 8.
PIC12(L)F1501 9.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC12(L)F1501 9.1 Independent Clock Source 9.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 27.0 “Electrical Specifications” for the LFINTOSC tolerances. The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds. 9.4 9.
PIC12(L)F1501 9.
PIC12(L)F1501 TABLE 9-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 OSCCON Bit 6 — Bit 5 Bit 4 Bit 3 IRCF<3:0> Bit 2 Bit 1 — Bit 0 SCS<1:0> Register on Page 49 STKOVF STKUNF — RWDT RMCLR RI POR BOR STATUS — — — TO PD Z DC C 17 WDTCON — — SWDTEN 77 PCON Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
PIC12(L)F1501 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs).
PIC12(L)F1501 10.2.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored.
PIC12(L)F1501 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PC +3 PC+3 PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 5 PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(P
PIC12(L)F1501 10.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC12(L)F1501 10.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2.
PIC12(L)F1501 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC12(L)F1501 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
2011-2015 Microchip Technology Inc. FIGURE 10-5: 7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES 6 0 7 4 PMADRH - rA r9 r8 r7 r6 3 0 7 PMADRL r5 r4 r3 r2 r1 r0 c3 c2 c1 - 5 - 0 7 PMDATH PMDATL 6 c0 Rev.
PIC12(L)F1501 FIGURE 10-6: FLASH MEMORY WRITE FLOWCHART Rev. 10-000049A 7/30/2013 Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row (word_cnt) Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Disable Interrupts (GIE = 0) Update the word counter (word_cnt--) Write Latches to Flash (LWLO = 0) Select Program or Config.
PIC12(L)F1501 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY (16 WRITE LATCHES) This write routine assumes the following: 1. 32 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC12(L)F1501 10.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC12(L)F1501 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2.
PIC12(L)F1501 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Rev. 10-000051A 7/30/2013 Start Verify Operation This routine assumes that the last row of data written was from an image saved on RAM.
PIC12(L)F1501 10.
PIC12(L)F1501 REGISTER 10-5: U-1 (1) — PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6 CFG
PIC12(L)F1501 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before s
PIC12(L)F1501 11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: Rev. 10-000052A 7/30/2013 • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Some ports may have one or more of the following additional registers.
PIC12(L)F1501 11.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 11-1. For this device family, the following functions can be moved between different pins. • • • • • These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.
PIC12(L)F1501 11.3 PORTA Registers 11.3.1 DATA REGISTER PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC12(L)F1501 11.
PIC12(L)F1501 REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented:
PIC12(L)F1501 REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(3) 1 = Pull-up enabl
PIC12(L)F1501 12.0 INTERRUPT-ON-CHANGE The PORTA pins can be configured to operate as Interrupt-on-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt.
PIC12(L)F1501 FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) Rev. 10-000 037A 6/2/201 4 IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D data bus = 0 or 1 Q D S to data bus IOCAFx Q write IOCAFx R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q4 Q4Q1 Q1 Q3 Q4 Q4Q1 DS40001615C-page 102 Q4 Q4Q1 Q4Q1 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 12.
PIC12(L)F1501 TABLE 12-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 99 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 64 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 103 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 103 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 103 TRISA — — TRISA5 TRISA4 —(1)
PIC12(L)F1501 13.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with a nominal output level (VFVR) of 1.024V. The output of the FVR can be configured to supply a reference voltage to the following: • ADC input channel • Comparator positive input • Comparator negative input The FVR can be enabled by setting the FVREN bit of the FVRCON register. 13.
PIC12(L)F1501 TABLE 13-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral Conditions Description HFINTOSC FOSC<2:0> = 010 and IRCF<3:0> = 000x INTOSC is active and device is not in Sleep. BOREN<1:0> = 11 BOR always enabled. BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled.
PIC12(L)F1501 13.
PIC12(L)F1501 14.0 TEMPERATURE INDICATOR MODULE FIGURE 14-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. Rev.
PIC12(L)F1501 TABLE 14-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR>1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 107 Shaded cells are unused by the temperature indicator module. 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 15.0 approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 15-1 shows the block diagram of the ADC. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit.
PIC12(L)F1501 15.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 15.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 11.
PIC12(L)F1501 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<2:0 > 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 100 ns 125 ns 250 ns 500 ns 2.0 s Fosc/4 100 200 ns 250 ns 500 ns 1.0 s 4.0 s Fosc/8 001 400 ns 500 ns 1.0 s 2.0 s 8.0 s Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s 32.0 s Fosc/64 110 3.2 s 4.0 s 8.0 s 16.
PIC12(L)F1501 15.1.5 INTERRUPTS 15.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC12(L)F1501 15.2 15.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 15.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.6 “ADC Conversion Procedure”. COMPLETION OF A CONVERSION 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep.
PIC12(L)F1501 15.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) • Disable weak pull-ups either globally (Refer to the OPTION_REG register) or individually (Refer to the appropriate WPUx register).
PIC12(L)F1501 15.
PIC12(L)F1501 REGISTER 15-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 bit 7 R/W-0/0 ADPREF<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified.
PIC12(L)F1501 REGISTER 15-3: R/W-0/0 ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 TRIGSEL<3:0> R/W-0/0 (1) U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) 0000 = No auto-conversion trigger selected 0001 = Reserved 0010 = Re
PIC12(L)F1501 REGISTER 15-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 15-5: R/W-x/u A
PIC12(L)F1501 REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC12(L)F1501 15.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-4.
PIC12(L)F1501 FIGURE 15-4: ANALOG INPUT MODEL Rev. 10-000070A 8/2/2013 VDD RS Analog Input pin VT § 0.6V RIC 1K Sampling switch SS RSS ILEAKAGE(1) VA Legend: CHOLD CPIN ILEAKAGE RIC RSS SS VT Note 1: CPIN 5pF CHOLD = 10 pF VT § 0.
PIC12(L)F1501 TABLE 15-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM ADCON2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> ADCS<2:0> TRIGSEL<3:0> Bit 1 Bit 0 Register on Page GO/DONE ADON 116 — — ADPREF<1:0> 117 — — — 118 — ADRESH ADC Result Register High 119, 120 ADRESL ADC Result Register Low 119, 120 ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 99 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 64 PIE1 TMR1GIE ADIE — — — — T
PIC12(L)F1501 16.0 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels.
PIC12(L)F1501 16.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACxCON1 register. The DAC output voltage can be determined by using Equation 16-1. 16.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value.
PIC12(L)F1501 16.
PIC12(L)F1501 17.0 COMPARATOR MODULE 17.1 Comparator Overview Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
PIC12(L)F1501 FIGURE 17-2: SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ • • • • CxIN+ analog pin DAC1_output FVR_buffer2 VSS See Section 13.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 16.0 “5-Bit Digital-to-Analog Converter (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. 17.2.3 Output Note: 17.
PIC12(L)F1501 17.2.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 17-2 shows the output state versus input conditions, including polarity control. TABLE 17-2: COMPARATOR OUTPUT STATE VS.
PIC12(L)F1501 17.4 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: See Section 27.
PIC12(L)F1501 17.
PIC12(L)F1501 REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 CxPCH<1:0> U-0 R/W-0/0 R/W-0/0 R/W-0/0 CxNCH<2:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt fla
PIC12(L)F1501 TABLE 17-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 ANSELA Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 99 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 131 CM1CON1 C1NTP C1INTN — — — — — — — MC1OUT 132 DACEN — DACOE1 DACOE2 — DACPSS — — 126 CMOUT DAC1CON0 C1PCH<1:0> — — — FVRCON FVREN FVRRDY TSEN TSRNG INTCON DAC1CON1 — C1NCH<2:0> 132 DACR<4:0> CDAFVR<1
PIC12(L)F1501 18.0 18.1.2 TIMER0 MODULE 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’.
PIC12(L)F1501 18.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC12(L)F1501 18.
PIC12(L)F1501 19.
PIC12(L)F1501 19.1 Timer1 Operation 19.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC12(L)F1501 19.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 19.4 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized.
PIC12(L)F1501 19.5.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 19.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 19.5.
PIC12(L)F1501 19.6 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register 19.7.
PIC12(L)F1501 FIGURE 19-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 19-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N DS40001615C-page 142 N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 19-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS40001615C-page 144 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL N+4 Cleared by software 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 19.
PIC12(L)F1501 REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TM
PIC12(L)F1501 TABLE 19-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 99 APFCON CWG1BSEL CWGA1SEL — — T1GSEL — CLC1SEL NCO1SEL 96 INTCON PIE1 PIR1 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 64 TMR1GIE ADIE — — — — TMR2IE TMR1IE 65 TMR1GIF ADIF — — — — TMR2IF TMR1IF TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
PIC12(L)F1501 20.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2 See Figure 20-1 for a block diagram of Timer2. FIGURE 20-1: TIMER2 BLOCK DIAGRAM Rev.
PIC12(L)F1501 20.1 Timer2 Operation 20.3 Timer2 Output The clock input to the Timer2 module is the system instruction clock (FOSC/4). The output of TMR2 is T2_match. T2_match is available to the following peripherals: TMR2 increments from 00h on each clock edge. • Configurable Logic Cell (CLC) • Numerically Controlled Oscillator (NCO) • Pulse Width Modulator (PWM) A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options.
PIC12(L)F1501 20.
PIC12(L)F1501 21.0 Figure 21-1 shows a simplified block diagram of PWM operation. PULSE-WIDTH MODULATION (PWM) MODULE For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 21.1.9 “Setup for PWM Operation using PWMx Pins”.
PIC12(L)F1501 21.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. Note: 21.1.1 Clearing the PWMxOE bit will relinquish control of the PWMx pin. FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle.
PIC12(L)F1501 21.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 21-4.
PIC12(L)F1501 21.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. 6. 7. 8. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the PR2 register with the PWM period value. Clear the PWMxDCH register and bits <7:6> of the PWMxDCL register. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register.
PIC12(L)F1501 21.
PIC12(L)F1501 REGISTER 21-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle.
PIC12(L)F1501 22.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 16 input signals, and through the use of configurable gates, reduces the 16 inputs to four logic lines that drive one of eight selectable single-output logic functions.
PIC12(L)F1501 22.1 each case, paired with a different group. This arrangement makes possible selection of up to two from a group without precluding a selection from another group. CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: • • • • Data selection is through four multiplexers as indicated on the left side of Figure 22-2. Data inputs in the figure are identified by a generic numbered input name.
PIC12(L)F1501 22.1.2 DATA GATING Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate.
PIC12(L)F1501 22.1.5 CLCx SETUP STEPS The following steps should be followed when setting up the CLCx: • Disable CLCx by clearing the LCxEN bit. • Select desired inputs using CLCxSEL0 and CLCxSEL1 registers (See Table 22-3). • Clear any associated ANSEL bits. • Set all TRIS bits associated with inputs. • Clear all TRIS bits associated with outputs. • Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers.
PIC12(L)F1501 FIGURE 22-2: LCx_in[0] INPUT DATA SELECTION AND GATING Data Selection 00000 Data GATE 1 LCx_in[31] lcxd1T LCxD1G1T lcxd1N LCxD1G1N 11111 LCxD2G1T LCxD1S<4:0> LCxD2G1N LCx_in[0] lcxg1 00000 LCxD3G1T lcxd2T LCxG1POL LCxD3G1N lcxd2N LCx_in[31] LCxD4G1T 11111 LCxD2S<4:0> LCx_in[0] LCxD4G1N 00000 Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N LCx_in[31] Data GATE 3 11111 lcxg3 LCxD3S<4:0> LCx_in[0] (Same as Data GATE 1) Data GATE 4 00000 lcxg4 lcxd4T (Same as
PIC12(L)F1501 FIGURE 22-3: PROGRAMMABLE LOGIC FUNCTIONS Rev.
PIC12(L)F1501 22.
PIC12(L)F1501 REGISTER 22-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0 =
PIC12(L)F1501 REGISTER 22-3: U-0 CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u LCxD2S<2:0>(1) — U-0 — R/W-x/u R/W-x/u R/W-x/u LCxD1S<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD2S<2:0>: Input Data 2 Selection Control bits(1) 111
PIC12(L)F1501 REGISTER 22-4: U-0 CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u (1) — LCxD4S<2:0> U-0 — R/W-x/u R/W-x/u R/W-x/u (1) LCxD3S<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 LCxD4S<2:0>: Input Data 4 Selection Control bits(1) 1
PIC12(L)F1501 REGISTER 22-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit 1 =
PIC12(L)F1501 REGISTER 22-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit 1 =
PIC12(L)F1501 REGISTER 22-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit 1 =
PIC12(L)F1501 REGISTER 22-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit 1 =
PIC12(L)F1501 REGISTER 22-9: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 — — — — — — MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit 2011-2015 Microchip Tech
PIC12(L)F1501 TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 99 CLC1CON LC1EN LC1OE LC1OUT LC1INTP LC1INTN CLCDATA — — — — — MLC3OUT MLC2OUT MLC1OUT 171 CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 167 CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 168 CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T
PIC12(L)F1501 23.0 NUMERICALLY CONTROLLED OSCILLATOR (NCO) MODULE The Numerically Controlled Oscillator (NCOx) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. The advantage of the addition method over simple counter driven timer is that the resolution of division does not vary with the divider value. The NCOx is most useful for applications that require frequency accuracy and fine resolution at a fixed duty cycle.
NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM NCOxINCH NCOxINCL Rev. 10-000028A 7/30/2013 16 (1) INCBUFH INCBUFL 16 NCO_overflow HFINTOSC 00 FOSC 01 LCx_out 10 20 Adder 20 NCOx_clk NCOxACCU NCOxACCH NCOxACCL 20 11 NCO1CLK NxCKS<1:0> NCO_interrupt set bit NCOxIF 2 Fixed Duty Cycle Mode Circuitry D Q D Status Q 0 _ 1 Q NxPFM NxOE TRIS bit NCOx NxPOL NCOx_out 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 23.2 Fixed Duty Cycle (FDC) Mode In Fixed Duty Cycle (FDC) mode, every time the accumulator overflows (NCO_overflow), the output is toggled. This provides a 50% duty cycle, provided that the increment value remains constant. For more information, see Figure 23-2. The FDC mode is selected by clearing the NxPFM bit in the NCOxCON register. 23.
NCO – FIXED DUTY CYCLE (FDC) AND PULSE FREQUENCY MODE (PFM) OUTPUT OPERATION DIAGRAM Rev. 10-000029A 11/7/2013 x k e x ent e x ator e erflow Status errupt 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 23.
PIC12(L)F1501 REGISTER 23-3: R/W-0/0 NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCOxACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxACC<7:0>: NCOx Accumulator, Low Byte REGISTER 23-4: R/W-0/0 NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH B
PIC12(L)F1501 REGISTER 23-6: R/W-0/0 NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 NCOxINC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCOxINC<7:0>: NCOx Increment, Low Byte Note 1: Write the NCOxINCH register first, then the NCOxINCL registe
PIC12(L)F1501 24.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources. 24.3 Selectable Input Sources The CWG generates the output waveforms from the input sources in Table 24-1.
SIMPLIFIED CWG BLOCK DIAGRAM Rev. 10-000123B 7/10/2015 GxASDLA 2 00 GxCS 1 FOSC 10 ‘1' 11 CWGxDBR cwg_clock GxASDLA = 01 6 HFINTOSC GxIS ‘0' Status C1OUT_async Reserved PWM1_out PWM2_out PWM3_out PWM4_out NCO1_out LC1_out = 0 R S TRISx Q GxOEA GxPOLA Input Source CWGxDBF R 6 Q GxOEB EN = 0 R 1 GxPOLB 00 CWG1FLT (INT pin) GxASDSFLT 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 24-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Dead Band Falling Edge Dead Band Rising Edge Dead Band Falling Edge Dead Band Rising Edge Dead Band CWGxB 24.5 Dead-Band Control Dead-band control provides for non-overlapping output signals to prevent shoot-through current in power switches. The CWG contains two 6-bit dead-band counters. One dead-band counter is used for the rising edge of the input source control.
2011-2015 Microchip Technology Inc.
PIC12(L)F1501 24.8 Dead-Band Uncertainty 24.9 Auto-Shutdown Control When the rising and falling edges of the input source triggers the dead-band counters, the input may be asynchronous. This will create some uncertainty in the deadband time delay. The maximum uncertainty is equal to one CWG clock period. Refer to Equation 24-1 for more detail. Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit.
PIC12(L)F1501 24.10 Operation During Sleep The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. The HFINTOSC remains active during Sleep, provided that the CWG module is enabled, the input source is active, and the HFINTOSC is selected as the clock source, regardless of the system clock source selected.
SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01) Shutdown Event Ceases GxASE Cleared by Software CWG Input Source Shutdown Source GxASE CWG1A Tri-State (No Pulse) CWG1B Tri-State (No Pulse) No Shutdown Output Resumes Shutdown Status FIGURE 24-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01) Shutdown Event Ceases GxASE auto-cleared by hardware CWG Input Source 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 24.
PIC12(L)F1501 REGISTER 24-2: R/W-x/u CWGxCON1: CWG CONTROL REGISTER 1 R/W-x/u GxASDLB<1:0> R/W-x/u R/W-x/u U-0 GxASDLA<1:0> — R/W-0/0 R/W-0/0 R/W-0/0 GxIS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB When an auto shutdown e
PIC12(L)F1501 REGISTER 24-3: CWGxCON2: CWG CONTROL REGISTER 2 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 GxASE GxARSEN — — — GxASDSC1 R/W-0/0 R/W-0/0 GxASDSFLT GxASDSCLC2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxASE: Auto-Shutdown Event Status bit 1 = An auto-shutdown ev
PIC12(L)F1501 REGISTER 24-4: CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING DEAD-BAND COUNT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u CWGxDBR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDBR
PIC12(L)F1501 TABLE 24-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH CWG Bit 7 ANSELA CWG1CON0 CWG1CON1 Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 99 G1OEB G1OEA G1POLB G1POLA — — G1CS0 187 G1ASDSCLC2 189 G1ASE G1ARSEN CWG1DBF — — CWG1DBR — — TRISA — — Legend: Note 1: Bit 4 G1EN G1ASDLB<1:0> CWG1CON2 Bit 5 G1ASDLA<1:0> — — — — G1ASDSC1 — G1IS<1:0> G1ASDSFLT CWG1DBF<5:0> 190 CWG1DBR<5:0> TRISA5 TRISA4 —(1) TRISA2 18
PIC12(L)F1501 25.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications.
PIC12(L)F1501 FIGURE 25-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Rev. 10-000128A 7/30/2013 Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins For additional interface recommendations, refer to your specific device programmer manual prior to PCB design.
PIC12(L)F1501 26.0 INSTRUCTION SET SUMMARY 26.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC12(L)F1501 FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k
PIC12(L)F1501 TABLE 26-3: ENHANCED MID-RANGE INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Cl
PIC12(L)F1501 TABLE 26-3: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED) 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG regist
PIC12(L)F1501 26.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] k Operands: 0 k 255 Operation: (W) .AND. (k) (W) Operation: FSR(n) + k FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.
PIC12(L)F1501 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC12(L)F1501 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC12(L)F1501 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC12(L)F1501 LSLF Logical Left Shift MOVF Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC12(L)F1501 MOVIW Move INDFn to W MOVLP Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Syntax: [ label ] MOVLP k Operands: 0 k 127 Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements)
PIC12(L)F1501 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged Status Affected: None Mode Syntax Preincremen
PIC12(L)F1501 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Return from subroutine.
PIC12(L)F1501 RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] RRF f,d SUBLW Syntax: [ label ] Operands: 0 k 255 Operation: k - (W) W) C, DC, Z The W register is subtracted (2’s complement method) from the 8-bit literal ‘k’. The result is placed in the W register. Operation: See description below Status Affected: Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag.
PIC12(L)F1501 SWAPF Swap Nibbles in f XORLW Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Operation: (W) .XOR. k W) Operation: Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’.
PIC12(L)F1501 NOTES: DS40001615C-page 208 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 27.0 ELECTRICAL SPECIFICATIONS 27.1 Absolute Maximum Ratings(†) Ambient temperature under bias...................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC12F1501 ..................................................................
PIC12(L)F1501 27.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC12LF1501 VDDMIN (Fosc 16 MHz).......................................................................................................... +1.8V VDDMIN (16 MHz < Fosc 20 MHz) ......................................................................................... +2.
PIC12(L)F1501 FIGURE 27-1: VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC12F1501 ONLY Rev. 10-000130A 8/6/2013 VDD (V) 5.5 2.5 2.3 0 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 27-8 for each Oscillator mode’s supported frequencies. FIGURE 27-2: VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC12LF1501 ONLY Rev. 10-000131A 8/5/2013 VDD (V) 3.6 2.5 1.
PIC12(L)F1501 27.3 DC Characteristics TABLE 27-1: SUPPLY VOLTAGE Standard Operating Conditions (unless otherwise stated) PIC12LF1501 PIC12F1501 Param. No. D001 Sym. VDD Characteristic Min. Typ† Max. Units VDDMIN 1.8 2.5 — — VDDMAX 3.6 3.6 V V FOSC 16 MHz FOSC 20 MHz 2.3 2.5 — — 5.5 5.5 V V FOSC 16 MHz FOSC 20 MHz 1.5 — — V Device in Sleep mode 1.7 — — V Device in Sleep mode — 1.6 — V — 1.6 — V — 0.8 — V — 1.5 — V -11 — +7 % 0.
PIC12(L)F1501 FIGURE 27-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(3) Note 1: 2: 3: TPOR(2) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 TABLE 27-2: SUPPLY CURRENT (IDD)(1,2) PIC12LF1501 Standard Operating Conditions (unless otherwise stated) PIC12F1501 Param. No. Device Characteristics D013 D013 D014 D014 D015 D015 Conditions Min. Typ† Max. Units VDD Note FOSC = 1 MHz, External Clock (ECM), Medium Power mode — 30 65 A 1.8 — 55 100 A 3.0 — 65 110 A 2.3 — 85 140 A 3.0 — 115 190 A 5.0 — 115 190 A 1.8 — 210 310 A 3.0 — 180 270 A 2.3 — 240 365 A 3.
PIC12(L)F1501 TABLE 27-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC12LF1501 Standard Operating Conditions (unless otherwise stated) PIC12F1501 Param. No. Device Characteristics Conditions Min. Typ† Max. Units VDD Note D019C — 1030 1500 A 3.0 FOSC = 20 MHz, External Clock (ECH), High-Power mode D019C — 1060 1600 A 3.0 — 1220 1800 A 5.0 FOSC = 20 MHz, External Clock (ECH), High-Power mode — 6 16 A 1.8 — 8 22 A 3.0 — 13 28 A 2.3 — 15 31 A 3.
PIC12(L)F1501 TABLE 27-3: POWER-DOWN CURRENTS (IPD)(1,2) PIC12LF1501 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC12F1501 Low-Power Sleep Mode, VREGPM = 1 Param. No. Device Characteristics Conditions Min. Typ† Max. +85°C Max. +125°C Units 0.020 1.0 8.0 A VDD D022 Base IPD — — 0.03 2.0 9.0 A 3.0 D022 Base IPD — 0.25 3.0 10 A 2.3 — 0.30 4.0 12 A 3.0 — 0.40 6.0 15 A 5.0 — 10 16 18 A 2.3 — 11 18 20 A 3.
PIC12(L)F1501 TABLE 27-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED) PIC12LF1501 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC12F1501 Low-Power Sleep Mode, VREGPM = 1 Param. No. Device Characteristics D026 D026 Min. Typ† Conditions Max. +85°C Max. +125°C Units VDD — 0.11 1.5 9.0 A 1.8 — 0.12 2.7 12 A 3.0 — 0.30 4.0 11 A 2.3 — 0.35 5.0 13 A 3.0 — 0.45 8.0 16 A 5.0 D026A* — 250 — — A 1.8 — 250 — — A 3.
PIC12(L)F1501 TABLE 27-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. VIL Characteristic Min. Typ† Max. Units — — Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V Input Low Voltage I/O PORT: D030 with TTL buffer D030A D032 MCLR VIH Input High Voltage I/O PORT: D040 with TTL buffer D040A D042 MCLR IIL D060 MCLR(2) IPUR D080 — V 4.5V VDD 5.5V — — V 1.8V VDD 4.5V 0.
PIC12(L)F1501 TABLE 27-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D112 VPBE VDD for Bulk Erase 2.7 — VDDMAX V D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V D114 IPPPGM Current on MCLR/VPP during Erase/Write — 1.
PIC12(L)F1501 27.4 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDIx do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 27-4: T Time osc rd rw sc ss t0 t1 wr CLKIN RD RD or WR SCKx SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Rev.
PIC12(L)F1501 FIGURE 27-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT mode) Note: TABLE 27-7: See Table 27-9. CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. Typ† Max. Units Conditions DC — 0.
PIC12(L)F1501 TABLE 27-8: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. OS08 Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units — MHz VDD = 3.0V, TA = 25°C, (Note 2) (Note 3) HFOSC Internal Calibrated HFINTOSC Frequency(1) ±2% — 16.0 OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time — — 5 15 s OS10A* TLFOSC ST LFINTOSC Wake-up from Sleep Start-up Time — — 0.
PIC12(L)F1501 FIGURE 27-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 27-9: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions TosH2ckL FOSC to CLKOUT(1) — — 70 ns 3.3V VDD 5.
PIC12(L)F1501 FIGURE 27-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O pins Note 1:Asserted low. DS40001615C-page 224 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 TABLE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions 2 — — s 10 16 27 ms VDD = 3.3V-5V, 1:512 Prescaler used Power-up Timer Period 40 65 140 ms PWRTE = 0 TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 s VBOR Brown-out Reset Voltage(1) 2.55 2.70 2.
PIC12(L)F1501 FIGURE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler With Prescaler TT0L 41* T0CKI Low Pulse Width No Prescaler With Prescaler Typ† Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.
PIC12(L)F1501 FIGURE 27-11: CLC PROPAGATION TIMING Rev. 10-000031A 7/30/2013 CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC01 CLC02 CLC03 Note 1: See FIGURE 22-1:, Configurable Logic Cell Block Diagram, to identify specific CLC signals. TABLE 27-12: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Sym.
PIC12(L)F1501 TABLE 27-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. Sym. No. Characteristic Min. Typ† Max. AD01 NR Resolution — — 10 AD02 EIL Integral Error — ±1 ±1.
PIC12(L)F1501 FIGURE 27-12: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 6 7 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 FIGURE 27-13: ADC CONVERSION TIMING (ADC CLOCK FROM FRC) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 Sampling Stopped Note 1:If the ADC clock source is selected
PIC12(L)F1501 TABLE 27-14: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Sym. No. AD130* TAD AD131 TCNV Characteristic Min. Typ† Max. Units ADC Clock Period (TADC) 1.0 — 6.0 ADC Internal FRC Oscillator Period (TFRC) 1.0 2.0 Conversion Time (not including Acquisition Time)(1) — 11 Conditions s FOSC-based 6.0 s ADCS<2:0> = x11 (ADC FRC mode) — TAD Set GO/DONE bit to conversion complete s AD132* TACQ Acquisition Time — 5.
PIC12(L)F1501 TABLE 27-16: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS(1) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. Sym. Characteristics Min. Typ. Max. Units — VDD/32 — V DAC01* CLSB Step Size DAC02* CACC Absolute Accuracy — — 1/2 LSb DAC03* CR Unit Resistor Value (R) — 5K — CST Time(2) — — 10 s DAC04* * Note 1: 2: Settling Comments These parameters are characterized but not tested. See Section 28.
PIC12(L)F1501 28.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC12(L)F1501 FIGURE 28-1: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC12LF1501 ONLY 14 Max. 12 10 IDD (µA) Typical 8 6 4 Max: 85°C + 3ı Typical: 25°C 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-2: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC12F1501 ONLY 25 Max. 20 IDD (µA) Typical 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-3: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC12LF1501 ONLY 50 45 Max: 85°C + 3ı Typical: 25°C 40 Max. 35 IDD (µA) 30 Typical 25 20 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-4: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC12F1501 ONLY 60 Max. 50 IDD (µA) 40 Typical 30 20 Max: 85°C + 3ı Typical: 25°C 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC12(L)F1501 FIGURE 28-5: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE, PIC12LF1501 ONLY 300 Typical: 25°C 250 4 MHz IDD (µA) 200 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-6: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE, PIC12LF1501 ONLY 350 Max: 85°C + 3ı 300 IDD (µA) 250 4 MHz 200 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-7: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE, PIC12F1501 ONLY 350 4 MHz Typical: 25°C 300 IDD (µA) 250 200 150 1 MHz 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 28-8: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE, PIC12F1501 ONLY 400 4 MHz Max: 85°C + 3ı 350 300 IDD (µA) 250 200 1 MHz 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001615C-page 236 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-9: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC12LF1501 ONLY 1.4 20 MHz Typical: 25°C 1.2 16 MHz IDD (mA) 1.0 0.8 0.6 8 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-10: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC12LF1501 ONLY ( ) 1.6 1.4 20 MHz Max: 85°C + 3ı 1.2 16 MHz IDD (mA) 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC12(L)F1501 FIGURE 28-11: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC12F1501 ONLY 1.4 20 MHz Typical: 25°C 1.2 16 MHz IDD (mA) 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 28-12: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC12F1501 ONLY 1.6 20 MHz Max: 85°C + 3ı 1.4 16 MHz 1.2 IDD (mA) 1.0 0.8 8 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC12(L)F1501 FIGURE 28-13: IDD, LFINTOSC, FOSC = 31 kHz, PIC12LF1501 ONLY 12 Max. Max: 85°C + 3ı Typical: 25°C 10 IDD (µA) 8 Typical 6 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-14: IDD, LFINTOSC, FOSC = 31 kHz, PIC12F1501 ONLY 25 Max. 20 IDD (µA) Typical 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-15: IDD, MFINTOSC, FOSC = 500 kHz, PIC12LF1501 ONLY 400 Max: 85°C + 3ı Typical: 25°C 350 Max. 300 IDD (µA) 250 Typical 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-16: IDD, MFINTOSC, FOSC = 500 kHz, PIC12F1501 ONLY 450 Max: 85°C + 3ı Typical: 25°C 400 Max. 350 Typical IDD (µA) 300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001615C-page 240 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-17: IDD TYPICAL, HFINTOSC, PIC12LF1501 ONLY 1.4 Typical: 25°C 1.2 16 MHz IDD (mA) 1.0 0.8 8 MHz 0.6 4 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-18: IDD MAXIMUM, HFINTOSC, PIC12LF1501 ONLY 1.6 Max: 85°C + 3ı 1.4 16 MHz IDD (mA) 1.2 1.0 8 MHz 0.8 4 MHz 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-19: IDD TYPICAL, HFINTOSC, PIC12F1501 ONLY 1.2 16 MHz 1.0 IDD (mA) 0.8 8 MHz 0.6 4 MHz 0.4 Typical: 25°C 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 28-20: IDD MAXIMUM, HFINTOSC, PIC12F1501 ONLY 1.4 1.2 16 MHz IDD (mA) 1.0 0.8 8 MHz 0.6 4 MHz 0.4 Max: 85°C + 3ı 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001615C-page 242 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-21: IPD BASE, LOW-POWER SLEEP MODE, PIC12LF1501 ONLY 450 Max: 85°C + 3 M 3ı Typical: 25°C 400 Max. 350 IPD D (nA) 300 250 200 150 100 Typical 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-22: IPD BASE, LOW-POWER SLEEP MODE, VREGPM = 1, PIC12F1501 ONLY 600 Max. Max: 85°C + 3ı Typical: 25°C 500 IPD (nA) 400 300 Typical 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-23: IPD, WATCHDOG TIMER (WDT), PIC12LF1501 ONLY 2.0 1.8 Max: 85°C + 3ı Typical: 25°C 1.6 Max. IPD (µA (µA) 1.4 1.2 1.0 0.8 08 0.6 Typical 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-24: IPD, WATCHDOG TIMER (WDT), PIC12F1501 ONLY 1.4 Max Max. 1.2 IPD (µA A) 1.0 0.8 Typical 0.6 0.4 Max: 85°C + 3ı Typical: 25°C 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC12(L)F1501 FIGURE 28-25: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12LF1501 ONLY 45 Max: 85°C + 3ı Typical: 25°C 40 35 Max. IPD (µA A) 30 Typical 25 20 15 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-26: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12F1501 ONLY 30 Max. 25 IPD (µA) 20 Typical 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-27: IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC12LF1501 ONLY 10 Max. 9 Max: 85°C + 3ı Typical: 25°C 8 7 Typical IPD D (µA) 6 5 4 3 2 1 0 16 1.6 1 1.8 8 2 2.0 0 2 2.2 2 2 2.4 4 2 2.6 6 2 2.8 8 3 3.0 0 3 3.2 2 3 3.4 4 3 3.6 6 3 3.8 8 VDD (V) FIGURE 28-28: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12LF1501 ONLY 12 Max. Max: 85°C + 3ı Typical: 25°C 10 8 IPD (µA) Typical 6 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC12(L)F1501 FIGURE 28-29: IPD, BROWN-OUT RESET (BOR), BORV = 0, PIC12F1501 ONLY 12 M Max. Max: 85°C + 3ı Typical: 25°C 10 8 IPD (µA) Typical 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.0 VDD (V) FIGURE 28-30: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12F1501 ONLY 14 Max Max. Max: 85°C + 3ı Typical: 25°C 12 IPD (µA) 10 Typical 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-31: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC12LF1501 ONLY 14 12 Max. IPD (µA) 10 8 Typical 6 4 Max: 85°C + 3ı Typical: 25°C 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-32: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC12F1501 ONLY 30 25 Max. IPD (µA) 20 Typical yp 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001615C-page 248 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-33: IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC12LF1501 ONLY 40 35 Max. 30 IPD (µA A) 25 20 Typical 15 10 Max: 85°C + 3ı Typical: 25 C 25°C 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-34: IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC12F1501 ONLY 60 50 Max. IPD (µA A) 40 30 Typical 20 Max: 85°C + 3ı Typical: 25°C 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-35: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC12F1501 ONLY 6 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 5 VOH (V) 4 Min. (-40°C) 3 Typical (25°C) 2 Max. (125°C) 1 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 IOH (mA) FIGURE 28-36: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC12F1501 ONLY 5 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 4 Max. (125°C) VOL (V) Typical (25°C) 3 Min.
PIC12(L)F1501 FIGURE 28-37: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 3.0 VOH (V) 2.5 2.0 1.5 1.0 Min. (-40°C) Typical (25°C) Max. (125°C) 0.5 0.0 -15 -13 -11 -9 -7 -5 -3 -1 IOH (mA) FIGURE 28-38: VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V 3.0 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 2.5 VOL (V) 2.0 Max. (125°C) Typical (25°C) Min. (-40°C) 1.5 1.0 0.5 0.
PIC12(L)F1501 FIGURE 28-39: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC12LF1501 ONLY 2.0 1.8 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 1.6 VOH (V) 1.4 1.2 Min. (-40°C) Max. (125°C) Typical (25°C) 1.0 0.8 0.6 0.4 0.2 0.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IOH (mA) FIGURE 28-40: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC12LF1501 ONLY 1.8 Max: 125°C + 3ı Typical: 25°C Min: -40°C - 3ı 1.6 1.4 VOL (V) 1.2 1.0 0.8 Max. (125°C) Min. (-40°C) Typical (25°C) 0.6 0.
PIC12(L)F1501 FIGURE 28-41: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 Voltage (V) 1.64 Typical 1.62 Min. 1.60 1.58 1.56 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.54 1.52 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 28-42: POR REARM VOLTAGE, PIC12F1501 ONLY 1.54 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.52 1.50 Max. Voltage (V) 1.48 1.46 1.44 Typical 1.42 1.40 Min. 1.38 1.36 1.
PIC12(L)F1501 FIGURE 28-43: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC12LF1501 ONLY 2.00 Max. Voltage (V) 1.95 Typical 1.90 1.85 Min. Max: Typical + 3ı Min: Typical - 3ı 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 28-44: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC12LF1501 ONLY 60 50 Max. Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı Voltage (mV) 40 Typical 30 20 Min.
PIC12(L)F1501 FIGURE 28-45: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC12F1501 ONLY 2.60 Max. 2.55 Voltage (V) 2.50 Typical 2.45 Min. 2.40 Max: Typical + 3ı Min: Typical - 3ı 2.35 2.30 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 28-46: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC12F1501 ONLY 70 Max. 60 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı Voltage (mV) 50 40 Typical 30 20 Min.
PIC12(L)F1501 FIGURE 28-47: BROWN-OUT RESET VOLTAGE, BORV = 0 2.80 2.75 Voltage (V) Max. 2.70 Typical 2.65 Min. Max: Typical + 3ı Min: Typical - 3ı 2.60 2.55 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) DS40001615C-page 256 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-48: LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0 2.50 Max. Max: Typical + 3ı Min: Typical - 3ı 2.40 Voltage (V) 2.30 Typical 2.20 2.10 2.00 Min. 1.90 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 120 140 Temperature (°C) FIGURE 28-49: LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0 45 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 40 35 Max. Typical Voltage (mV) 30 25 Min.
PIC12(L)F1501 FIGURE 28-50: WDT TIME-OUT PERIOD 24 22 Max. Time (ms) 20 18 Typical 16 Min. 14 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 28-51: PWRT PERIOD 100 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 90 Max. Time (ms) 80 70 Typical 60 Min. 50 40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC12(L)F1501 FIGURE 28-52: FVR STABILIZATION PERIOD 60 Max: Typical + 3ı Typical: statistical mean @ 25°C 50 Max. Time (us) 40 Typical 30 20 Note: The FVR Stabilization Period applies when: 1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices. 2) when exiting sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices In all other cases, the FVR is stable when released from RESET. 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.
PIC12(L)F1501 FIGURE 28-53: COMPARATOR HYSTERESIS, NORMAL POWER MODE (CxSP = 1, CxHYS = 1) 40 35 Max. Hysteresis (mV) 30 25 Typical 20 15 Min. 10 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 28-54: COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1) 8 7 Max. Hysteresis (mV) 6 5 Typical 4 3 2 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1 Min. 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC12(L)F1501 FIGURE 28-55: COMPARATOR RESPONSE TIME, NORMAL POWER MODE (CxSP = 1) 350 300 Time (ns) 250 Max. 200 Typical 150 100 Max: Typical + 3ı Typical: 25°C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 28-56: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL POWER MODE (CxSP = 1) 400 Max: 125°C + 3ı Typical: 25°C Min: -45°C - 3ı 350 Time (ns) 300 250 Max. (125°C) 200 150 Typical (25°C) 100 Min. (-40°C) 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC12(L)F1501 FIGURE 28-57: COMPARATOR INPUT OFFSET AT 25°C, NORMAL POWER MODE (CxSP = 1), PIC12F1501 ONLY 50 40 30 Max. Offset Voltage (mV) 20 10 Typical 0 Min. -10 -20 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı -30 -40 -50 0.0 1.0 2.0 3.0 4.0 5.0 Common Mode Voltage (V) DS40001615C-page 262 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-58: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC12LF1501 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 Min. 26 24 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 28-59: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC12F1501 ONLY 36 34 Max. Frequency (kHz) 32 30 Typical 28 26 Min.
PIC12(L)F1501 FIGURE 28-60: HFINTOSC ACCURACY OVER TEMPERATURE, VDD = 1.8V, PIC12LF1501 ONLY 8% 6% Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı Accuracy (%) 4% Max. 2% 0% Typical -2% -4% Min. -6% -8% -10% -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) HFINTOSC ACCURACY OVER TEMPERATURE, 2.3V VDD 5.5V FIGURE 28-61: 8% 6% Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı Accuracy (%) 4% Max. 2% Typical 0% -2% Min.
PIC12(L)F1501 FIGURE 28-62: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, PIC12LF1501 ONLY 5.0 4.5 Max. 4.0 Time (us) 3.5 Typical 3.0 2.5 2.0 1.5 Max: 85°C + 3ı Typical: 25°C 1.0 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 FIGURE 28-63: LOW-POWER SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 1, PIC12F1501 ONLY 35 Max. 30 Typical Time (us) 25 20 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 28-64: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 0, PIC12F1501 ONLY 12 Max. 10 Time (us) 8 Typical 6 4 Max: 85°C + 3ı Typical: 25°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC12(L)F1501 29.
PIC12(L)F1501 29.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC12(L)F1501 29.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC12(L)F1501 29.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC12(L)F1501 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) e3 * Note: * 12F1501 I/P e3 017 1110 Example 12F1501 I/SN1110 017 NNN Legend: XX...
PIC12(L)F1501 Package Marking Information (Continued) 8-Lead MSOP (3x3 mm) Example F1501I 110017 8-Lead DFN (2x3x0.9 mm) 8-Lead UDFN (2x3x0.5 mm) Example BAK 110 10 8-Lead DFN (3x3x0.9 mm) Example XXXX YYWW NNN MFB1 1110 017 PIN 1 DS40001615C-page 272 PIN 1 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 TABLE 30-1: 8-LEAD 2x3 DFN (MC) TOP MARKING Part Number PIC12F1501-E/MC Marking BAK PIC12F1501-I/MC BAL PIC12LF1501-E/MC BAM PIC12LF1501-I/MC BAP TABLE 30-2: 8-LEAD 3x3 DFN (MF) TOP MARKING Part Number PIC12F1501-E/MF Marking MFA1 PIC12F1501-I/MF MFB1 PIC12LF1501-E/MF MFC1 PIC12LF1501-I/MF MFD1 TABLE 30-3: 8-LEAD 2X3 UDFN (MU) TOP MARKING Part Number Marking PIC12F1501-E/MU BAR PIC12F1501-I/MU BAQ PIC12LF1501-E/MU BAT PIC12LF1501-I/MU BAS 2011-2015 Microchip T
PIC12(L)F1501 30.2 Package Details The following sections give the technical details of the packages. 4 ' ( "' # ' 5 $ + ") " " ' 5 & ' ' $ ' '' 366+++ ( (6 5 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 7 '" ( " : ( '" 8#(* & " 8-9/ 8 8 ' < = ' ' 8; 2 - > > .
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001615C-page 276 2011-2015 Microchip Technology Inc.
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PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001615C-page 278 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001615C-page 280 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 ( $ ) * +' ,- - %& ( 4 ' ( "' # ' 5 $ + ") " " ' 5 & ' ' $ ' '' 366+++ ( (6 5 e D b N N L K E2 E EXPOSED PAD NOTE 1 NOTE 1 2 1 2 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 7 '" ( " : ( '" 8#(* & " :: / / 8 8 8; < = ' ;! 9 ' = ' $ && - ' ' 5 "" 2 -
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001615C-page 282 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001615C-page 284 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 ( $ ) * +. ,- - %/ . ( 4 ' ( "' # ' 5 $ + ") " " ' 5 & ' ' $ ' '' 366+++ ( (6 5 DS40001615C-page 286 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 ( $ ) * +. ,- - %/ . ( 4 ' ( "' # ' 5 $ + ") " " ' 5 & ' ' $ ' '' 366+++ ( (6 5 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (11/2011) Original release. Revision B (04/2014) Updated Electrical Specifications and added Characterization Data; Added UDFN package. Revision C (10/2015) Added Section 3.2 High Endurance Flash. Updated Equation 15-1; Figure 24-1; Register 24-3; Sections 22.1.5, 24.9.1.2, 24.11.1, and 27.1; and Tables 1-2, 3-5, and 24-2. Updated Product Identification System section. DS40001615C-page 288 2011-2015 Microchip Technology Inc.
PIC12(L)F1501 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers.
PIC12(L)F1501 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO.
PIC12(L)F1501 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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