Datasheet

Micrel, Inc. MIC4680
March 2008 12
M9999-032808
OUT
OUT
D
P
η
P
P −=
5W
0.79
5W
P
D
−=
1.33WP
D
=
Calculate the worst-case junction temperature:
T
J
= P
D(IC)
θ
JC
+ (T
C
– T
A
) + T
A(max)
where:
T
J
= MIC4680 junction temperature
P
D(IC)
= MIC4680 power dissipation
θ
JC
= junction-to-case thermal resistance.
The θ
JC
for the MIC4680’s power-SOIC-8
is approximately 20°C/W. (Also see Figure
1.)
T
C
= “pin” temperature measurement taken at
the entry point of pins 6 or 7 into the
plastic package at the ambient
temperature (T
A
) at which T
C
is measured.
T
A
= ambient temperature at which T
C
is
measured.
T
A(max)
= maximum ambient operating temp. for
the specific design.
Calculating the maximum junction temperature given a
maximum ambient temperature of 65°C:
TJ = 1.064 × 20°C/W + (45°C – 25°C) + 65°C
TJ = 106.3°C
This value is less than the allowable maximum operating
junction temperature of 125°C as listed in “Operating
Ratings.” Typical thermal shutdown is 160°C and is
listed in “Electrical Characteristics.”
Increasing the Maximum Output Current
The maximum output current at high input voltages can
be increased for a given board layout. The additional
three components shown in Figure 4 will reduce the
overall loss in the MIC4680 by about 20% at high V
IN
and high I
OUT
.
Even higher output current can be achieved by using the
MIC4680 to switch an external FET. See Figure 9 for a
5A supply with current limiting.
Layout Considerations
Layout is very important when designing any switching
regulator. Rapidly changing switching currents through
the printed circuit board traces and stray inductance can
generate voltage transients which can cause problems.
To minimize stray inductance and ground loops, keep
trace lengths, indicated by the heavy lines in Figure 5, as
short as possible. For example, keep D1 close to pin 3
and pins 5 through 8, keep L1 away from sensitive node
FB, and keep C
IN
close to pin 2 and pins 5 though 8. See
“Applications Information: Thermal Considerations” for
ground plane layout.
The feedback pin should be kept as far way from the
switching elements (usually L1 and D1) as possible.
A circuit with sample layouts is provided. See Figure 6a
through 6e.
SWIN
FB
GND
SHDN
D1
1N4148
2.2nF
MIC4680BM
5678
3
Figure 4. Increasing Maximum Output Current
at High Input Voltages
Load
SW
L1
68µH
IN
FB
GND
SHDN
C
OUT
R1
R2D1
V
OUT
MIC4680BM
GND
C
IN
V
IN
+4V to +34V
Power
SOIC-8
5678
4
32
1
Figure 5. Critical Traces for Layout
SW
L1
68µH
IN
FB
GND
SHDN
D1
B260A
or
SS26
J2
V
OUT
1A
J4
GND
U1 MIC4680BM
C2
0.1µF
50V
C1
15µF
35V
J1
V
IN
4V to +34V
J3
GND
SOIC-8 5–8
4
32
1
S1
NKK G12AP
ON
OFF
C4
220µF
10V
C3*
optional
C5
0.1µF
50V
R1
3.01k
R2
6.49k
JP1a
1.8V
R6
optional
R3
2.94k
R4
1.78k
R5
JP1b
2.5V
JP1c
3.3V
JP1d
5.0V
1
2
3
4
5
6
7
8
* C3 can be used to provide additional stability
and improved transient response.
Figure 6a. Evaluation Board Schematic Diagram