Datasheet
2018 Microchip Technology Inc. DS20006077A-page 11
MIC4416/7
4.0 FUNCTIONAL DESCRIPTION
Refer to the Functional Block Diagram.
The MIC4416 is a non-inverting driver. A logic high on
the CTL (control) input produces gate drive output. The
MIC4417 is an inverting driver. A logic low on the CTL
(control) input produces gate drive output. The G (gate)
output is used to turn on an external N-channel
MOSFET.
4.1 Supply
VS (supply) is rated for +4.5V to +18V. External
capacitors are recommended to decouple noise.
4.2 Control
CTL (control) is a TTL-compatible input. CTL must be
forced high or low by an external signal. A floating input
will cause unpredictable operation.
A high input turns on Q1, which sinks the output of the
0.3 mA and the 0.6 mA current source, forcing the input
of the first inverter low.
4.3 Hysteresis
The control threshold voltage, when CTL is rising, is
slightly higher than the control threshold voltage when
CTL is falling.
When CTL is low, Q2 is on, which applies the additional
0.6 mA current source to Q1. Forcing CTL high turns
on Q1 which must sink 0.9 mA from the two current
sources. The higher current through Q1 causes a
larger drain-to-source voltage drop across Q1. A
slightly higher control voltage is required to pull the
input of the first inverter down to its threshold.
Q2 turns off after the first inverter output goes high.
This reduces the current through Q1 to 0.3 mA. The
lower current reduces the drain-to-source voltage drop
across Q1. A slightly lower control voltage will pull the
input of the first inverter up to its threshold.
4.4 Drivers
The second (optional) inverter permits the driver to be
manufactured in inverting and non-inverting versions.
The last inverter functions as a driver for the output
MOSFETs Q3 and Q4.
4.5 Gate Output
G (gate) is designed to drive a capacitive load. V
G
(gate
output voltage) is either approximately the supply
voltage or approximately ground, depending on the
logic state applied to CTL.
If CTL is high, and VS (supply) drops to zero, the gate
output will be floating (unpredictable).
4.6 ESD Protection
D1 protects VS from negative ESD voltages. D2 and
D3 clamp positive and negative ESD voltages applied
to CTL. R1 isolates the gate of Q1 from sudden
changes on the CTL input. D4 and D5 prevent Q1’s
gate voltage from exceeding the supply voltage or
going below ground.