Datasheet

 2012-2018 Microchip Technology Inc. DS20002300C-page 37
MCP7951X/MCP7952X
6.2 Status Register
The STATUS register contains the BP<1:0>, WEL and
WIP bits. The STATUS register is accessed using the
SRREAD and SRWRITE instructions.
The Block Protection (BP<1:0>) bits are used to set the
block write protection for the EEPROM array according
to Tabl e 6-1 . These bits are set by the user issuing the
SRWRITE instruction. These bits are nonvolatile.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the nonvolatile memory, when set to a
‘0’, the latch prohibits writes to the nonvolatile memory.
The state of this bit can be updated via the EEWREN or
EEWRDI instructions. This bit is read-only.
The WIP bit indicates whether the MCP795XX is busy
with a nonvolatile memory write operation. When set to
a ‘1’, a write is in progress. When set to a ‘0’, no write
is in progress. This bit is read-only.
TABLE 6-1: BLOCK PROTECTION
REGISTER 6-1: STATUS: EEPROM WRITE PROTECTION REGISTER
6.2.1 STATUS REGISTER WRITE
SEQUENCE
The Write Status Register instruction (SRWRITE)
allows the user to write to the nonvolatile bits in the
STATUS register.
Prior to any attempt to write data to the STATUS
register, the write enable latch must be set by issuing
the EEWREN instruction. This is done by setting CS
low
and then clocking out the proper instruction into the
MCP795XX.
After all eight bits of the instruction are transmitted, CS
must be driven high to set the write enable latch. If the
write operation is initiated immediately after the
EEWREN instruction without CS driven high, data will not
be written to the array since the write enable latch was
not properly set. The device is selected by pulling CS
low. The 8-bit SRWRITE instruction is transmitted to the
MCP795XX followed by the 8-bit data byte. CS
is
driven high to end the operation and initiate the
nonvolatile write cycle (Figure 6-4).
BP1 BP0
Array Addresses
Write-Protected
00 None
01
Upper 1/4
60h-7Fh (MCP7951X)
C0h-FFh (MCP7952X)
10
Upper 1/2
40h-7Fh (MCP7951X)
80h-FFh (MCP7952X)
11 All
U-0 U-0 U-0 U-0 R/W R/W R-0 R-0
— — — — BP1 BP0 WEL WIP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is clear x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3-2 BP<1:0>: EEPROM Array Block Protection bits
Selects which EEPROM region is write-protected
00 = None
01 = Upper 1/4
10 = Upper 1/2
11 = All
bit 1 WEL: Write Enable Latch bit
Indicates whether or not nonvolatile memory writes are enabled. It is automatically cleared at the end
of a nonvolatile memory write cycle.
0 = Writes to nonvolatile memory are not enabled
1 = Writes to nonvolatile memory are enabled
bit 0 WIP: Write-In-Process bit
Indicates whether or not a nonvolatile memory write cycle is in process
0 = Nonvolatile write cycle is not in process
1 = Nonvolatile write cycle is in process