Datasheet

MCP7941X
DS22266A-page 16 Preliminary  2010 Microchip Technology Inc.
5.0 ON BOARD MEMORY
The MCP7941X has both on-board EEPROM memory
and Battery-Backed SRAM. The SRAM is arranged as
64 x 8 bytes and is retained when the V
CC supply is
removed, provided the V
BAT supply is present and
enabled. The EEPROM is organized as 128 x 8 bytes.
The EEPROM is nonvolatile memory and does not
require the V
BAT supply for retention.
5.1 SRAM
FIGURE 5-1: SRAM/RTCC BYTE WRITE
FIGURE 5-2: SRAM/RTCC MULTIPLE BYTE WRITE
The 64 bytes of user SRAM are at location 0x20h and
can be accessed during an RTCC update. Upon POR
the SRAM will be in an undefined state.
Writing to the SRAM and RTCC is accomplished in a
similar way to writing to the EEPROM (as described
later in this document) with the following consider-
ations:
• There is no page. The entire 64 bytes of SRAM or
32 bytes of RTCC register can be written in one
command.
• The SRAM allows an unlimited number of read/
write cycles with no cell wear out.
• The RTCC and SRAM are not accessible when
the device is running on the external V
BAT.
• The RTCC and SRAM are separate blocks. The
SRAM array may be accessed during an RTCC
update.
• Read and write access is limited to either the
RTCC register block or the SRAM array. The
Address Pointer will rollover to the start of the
addressed block.
• Data written to the RTCC and SRAM are on a per
byte basis.
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
BYTE
DATA
S
T
O
P
A
C
K
A
C
K
A
C
K
S 1101 0
1
11
P
x
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
BYTE
DATA BYTE 0
S
T
O
P
A
C
K
A
C
K
A
C
K
DATA BYTE N
A
C
K
S 1101 0
111
P
x
Note: Entering an address past 5F for an SRAM
operation will result in the MCP7941X not
acknowledging the address.