Datasheet

MCP6V01/2/3
DS22058C-page 6 © 2008 Microchip Technology Inc.
1.3 Timing Diagrams
FIGURE 1-1: Amplifier Start Up.
FIGURE 1-2: Offset Correction Settling
Time.
FIGURE 1-3: Output Overdrive Recovery.
FIGURE 1-4: Chip Select (MCP6V03).
1.4 Test Circuits
The circuits used for the DC and AC tests are shown in
Figure 1-5 and Figure 1-6. Lay the bypass capacitors
out as discussed in Section 4.3.8 “Supply Bypassing
and Filtering”. R
N
is equal to the parallel combination
of R
F
and R
G
to minimize bias current effects.
FIGURE 1-5: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-6: AC and DC Test Circuit for
Most Inverting Gain Conditions.
The circuit in Figure 1-7 tests the op amp input’s
dynamic behavior (i.e., IMD, t
STR
, t
STL
and t
ODR
). The
potentiometer balances the resistor network (V
OUT
should equal V
REF
at DC). The op amp’s common
mode input voltage is V
CM
=V
IN
/2. The error at the
input (V
ERR
) appears at V
OUT
with a noise gain of
10 V/V.
FIGURE 1-7: Test Circuit for Dynamic
Input Behavior.
V
DD
V
OS
V
OS
+50µV
V
OS
–50µV
t
STR
0V
1.8V to 5.5V
1.8V
V
IN
V
OS
V
OS
+50µV
V
OS
+50µV
t
STL
V
IN
V
OUT
V
DD
V
SS
t
ODR
t
ODR
V
DD
/2
V
IL
High-Z
t
ON
V
IH
CS
t
OFF
V
OUT
-2 µA
High-Z
I
SS
-2 µA
300 µA
1µA
I
DD
1µA
300 µA
V
DD
/5 MΩ
I
CS
V
DD
/5 MΩ
5pA
(typical)
(typical)
(typical) (typical)
(typical) (typical)
(typical)
(typical)
(typical)
V
DD
MCP6V0X
R
G
R
F
R
N
V
OUT
V
IN
V
DD
/3
1µF
C
L
R
L
V
L
100 nF
R
ISO
V
DD
MCP6V0X
R
G
R
F
R
N
V
OUT
V
DD
/3
V
IN
1µF
C
L
R
L
V
L
100 nF
R
ISO
V
DD
MCP6V0X
V
OUT
1µF
C
L
R
L
V
L
100 nF
R
ISO
20.0 kΩ
24.9 Ω
20.0 kΩ 50Ω
V
IN
V
REF
0.1%
0.1% 25 turn
20.0 kΩ
20.0 kΩ
0.1%
0.1%
2.49 kΩ 2.49 kΩ