Datasheet

 2009-2011 Microchip Technology Inc. DS22140B-page 11
MCP6L01/1R/1U/2/4
4.0 APPLICATION INFORMATION
The MCP6L01/1R/1U/2/4 family of op amps is manu-
factured using Microchip’s state of the art CMOS
process. It is designed for low cost, low power and
general purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6L01/1R/1U/2/4 ideal for battery-powered
applications. This device has high phase margin, which
makes it stable for larger capacitive load applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The MCP6L01/1R/1U/2/4 op amps are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-10 shows an input
voltage exceeding both supplies without any phase
reversal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit they are in must limit the
currents (and voltages) at the input pins (see
Section 1.1 “Absolute Maximum Ratings †”).
Figure 4-1 shows the recommended approach to
protecting these inputs. The internal ESD diodes
prevent the input pins (V
IN
+ and V
IN
–) from going too
far below ground, and the resistors R
1
and R
2
limit the
possible current drawn out of the input pins. Diodes D
1
and D
2
prevent the input pins (V
IN
+ and V
IN
–) from
going too far above V
DD
, and dump any currents onto
V
DD
.
FIGURE 4-1: Protecting the Analog
Inputs.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
CM
) is below ground (V
SS
); see
Figure 2-7. Applications that are high impedance may
need to limit the usable voltage range.
4.1.3 NORMAL OPERATION
The input stage of the MCP6L01/1R/1U/2/4 op amps
use two differential CMOS input stages in parallel. One
operates at low common mode input voltage (V
CM
),
while the other operates at high V
CM
. With this
topology, and at room temperature, the device
operates with V
CM
up to 0.3V above V
DD
and 0.3V
below V
SS
(typically at +25°C).
The transition between the two input stages occurs
when V
CM
=V
DD
– 1.1V. For the best distortion and
gain linearity, with noninverting gains, avoid this region
of operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6L01/1R/1U/2/4
op amps is V
DD
– 35 mV (minimum) and V
SS
+35mV
(maximum) when R
L
=10k is connected to V
DD
/2
and V
DD
= 5.0V. Refer to Figure 2-13 for more informa-
tion.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (R
ISO
in Figure 4-2) improves the
feedback loop’s stability by making the output load
resistive at higher frequencies; the bandwidth will
usually be decreased.
FIGURE 4-2: Output Resistor, R
ISO
stabilizes large capacitive loads.
Bench measurements are helpful in choosing R
ISO
.
Adjust R
ISO
so that a small signal step response (see
Figure 2-14) has reasonable overshoot (e.g., 4%).
V
1
MCP6L0X
R
1
V
DD
D
1
R
1
>
V
SS
– (minimum expected V
1
)
2mA
R
2
>
V
SS
– (minimum expected V
2
)
2mA
V
2
R
2
D
2
R
3
R
ISO
V
OUT
C
L
MCP6L0X
R
F
R
G
R
N