Datasheet

© 2007 Microchip Technology Inc. DS21812E-page 13
MCP6291/1R/2/3/4/5
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (R
ISO
in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-3: Output Resistor, R
ISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit's noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
FIGURE 4-4: Recommended R
ISO
Values
for Capacitive Loads.
After selecting R
ISO
for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6291/1R/2/3/4/5 SPICE
macro model are helpful.
4.4 MCP629X Chip Select
The MCP6293 and MCP6295 are single and dual op
amps with Chip Select (CS
), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typical)
and flows through the CS pin to V
SS
. When this
happens, the amplifier output is put into a high-imped-
ance state. By pulling CS
low, the amplifier is enabled.
The CS
pin has an internal 5 MΩ (typical) pull-down
resistor connected to V
SS
, so it will go low if the CS pin
is left floating. Figure 1-1 shows the output voltage and
supply current response to a CS
pulse.
4.5 Cascaded Dual Op Amps
(MCP6295)
The MCP6295 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
device in Low-power mode. Refer to Section 4.4
“MCP629X Chip Select”.
FIGURE 4-5: Cascaded Gain Amplifier.
The output of op amp A is loaded by the input imped-
ance of op amp B, which is typically 10
13
Ω||6pF, as
specified in the DC specification table (Refer to
Section 4.3 “Capacitive Loads” for further details
regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as V
SS
– 300 mV and
V
DD
+ 300 mV. However, since the output of op amp A
is limited to V
OL
and V
OH
(20 mV from the rails with a
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
V
SS
+ 20 mV and V
DD
–20mV.
V
IN
R
ISO
V
OUT
C
L
–
+
MCP629X
10
100
10 100 1,000 10,000
Normalized Load Capacitance; C
L
/G
N
(pF)
Recommended R
ISO
(Ω)
G
N
= 1 V/V
G
N
≥ 2 V/V
A
B
CS
2
3
5
6
7
V
INA+
V
OUTB
MCP6295
1
V
INA–
V
OUTA
/V
INB+
V
INB–