Datasheet
MCP6291/1R/2/3/4/5
DS21812E-page 12 © 2007 Microchip Technology Inc.
4.0 APPLICATION INFORMATION
The MCP6291/1R/2/3/4/5 family of op amps is
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low-cost, low-power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
makes the MCP6291/1R/2/3/4/5 ideal for battery-pow-
ered applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The MCP6291/1R/2/3/4/5 op amp is designed to
prevent phase reversal when the input pins exceed the
supply voltages. Figure 2-32 shows the input voltage
exceeding the supply voltage without any phase rever-
sal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (I
B
). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
SS
. They also clamp any voltages that go too far
above V
DD
; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the V
IN
+ and V
IN
– pins (see
Absolute Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(V
IN
+ and V
IN
–) from going too far below ground, and
the resistors R
1
and R
2
limit the possible current drawn
out of the input pins. Diodes D
1
and D
2
prevent the
input pins (V
IN
+ and V
IN
–) from going too far above
V
DD
, and dump any currents onto V
DD
. When
implemented as shown, resistors R
1
and R
2
also limit
the current through D
1
and D
2
.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R
1
and R
2
. In this case, the currents through
the diodes D
1
and D
2
need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
IN
+ and
V
IN
–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (V
CM
) is below
ground (V
SS
); see Figure 2-31. Applications that are
high impedance may need to limit the usable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of the MCP6291/1R/2/3/4/5 op amps
use two differential CMOS input stages in parallel. One
operates at low common mode input voltage (V
CM
),
while the other operates at high V
CM
. WIth this topol-
ogy, the device operates with V
CM
up to 0.3V past
either supply rail. The input offset voltage (V
OS
) is mea-
sured at V
CM
= V
SS
- 0.3V and V
DD
+ 0.3V to ensure
proper operation.
The transition between the two input stages occurs
when V
CM
= V
DD
- 1.1V. For the best distortion and gain
linearity, with non-inverting gains, avoid this region of
operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6291/1R/2/3/4/5
op amp is V
DD
– 15 mV (min.) and V
SS
+15mV
(maximum) when R
L
=10kΩ is connected to V
DD
/2
and V
DD
= 5.5V. Refer to Figure 2-16 for more
information.
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
–
V
1
MCP629X
R1
V
DD
D1
R
1
>
V
SS
– (minimum expected V1)
2mA
V
OUT
R
2
>
V
SS
– (minimum expected V2)
2mA
V
2
R2
D2