Datasheet

MCP6001/1R/1U/2/4
DS21733J-page 16 © 2009 Microchip Technology Inc.
4.7.3 PEAK DETECTOR
The MCP6001/2/4 op amp has a high input impedance,
rail-to-rail input/output and low input bias current, which
makes this device suitable for peak detector
applications. Figure 4-9 shows a peak detector circuit
with clear and sample switches. The peak-detection
cycle uses a clock (CLK), as shown in Figure 4-9.
At the rising edge of CLK, Sample Switch closes to
begin sampling. The peak voltage stored on C
1
is
sampled to C
2
for a sample time defined by t
SAMP
. At
the end of the sample time (falling edge of Sample
Signal), Clear Signal goes high and closes the Clear
Switch. When the Clear Switch closes, C
1
discharges
through R
1
for a time defined by t
CLEAR
. At the end of
the clear time (falling edge of Clear Signal), op amp A
begins to store the peak value of V
IN
on C
1
for a time
defined by t
DETECT
.
In order to define t
SAMP
and t
CLEAR
, it is necessary to
determine the capacitor charging and discharging
period. The capacitor charging time is limited by the
amplifier source current, while the discharging time (
τ)
is defined using R
1
(τ = R
1
C
1
). t
DETECT
is the time that
the input signal is sampled on C
1
and is dependent on
the input voltage change frequency.
The op amp output current limit, and the size of the
storage capacitors (both C
1
and C
2
), could create
slewing limitations as the input voltage (V
IN
) increases.
Current through a capacitor is dependent on the size of
the capacitor and the rate of voltage change. From this
relationship, the rate of voltage change or the slew rate
can be determined. For example, with an op amp short
circuit current of I
SC
= 25 mA and a load capacitor of
C
1
= 0.1 µF, then:
EQUATION 4-1:
This voltage rate of change is less than the MCP6001/2/4
slew rate of 0.6 V/µs. When the input voltage swings
below the voltage across C
1
, D
1
becomes reverse-
biased. This opens the feedback loop and rails the
amplifier. When the input voltage increases, the amplifier
recovers at its slew rate. Based on the rate of voltage
change shown in the above equation, it takes an
extended period of time to charge a 0.1 µF capacitor. The
capacitors need to be selected so that the circuit is not
limited by the amplifier slew rate. Therefore, the
capacitors should be less than 40 µF and a stabilizing
resistor (R
ISO
) needs to be properly selected. (Refer to
Section 4.3 “Capacitive Loads”).
FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches.
dV
C1
dt
------------ -
I
SC
C
1
------- -=
25mA
0.1μF
---------------=
dV
C1
dt
------------ - 250mV μs⁄=
I
SC
C
1
dV
C1
dt
------------ -
=
V
IN
MCP6002
V
C1
MCP6002
D
1
Op Amp A
Op Amp B
V
OUT
MCP6001
Op Amp C
C
2
Sample Signal
Clear Signal
Clear
R
ISO
Sample
–
+
–
+
–
+
CLK
t
SAMP
t
CLEAR
t
DETECT
Switch
Switch
1/2
1/2
R
1
R
ISO
V
C2
C
1