Datasheet

MCP4921/4922
DS21897A-page 18  2004 Microchip Technology Inc.
5.0 SERIAL INTERFACE
5.1 Overview
The MCP492X family is designed to interface directly
with the Serial Peripheral Interface (SPI) port, available
on many microcontrollers, and supports Mode 0,0 and
Mode 1,1. Commands and data are sent to the device
via the SDI pin, with data being clocked-in on the rising
edge of SCK. The communications are unidirectional
and, thus, data cannot be read out of the MCP492X.
The CS
pin must be held low for the duration of a write
command. The write command consists of 16 bits and
is used to configure the DAC’s control and data latches.
Register 5-1 details the input registers used to config-
ure and load the DAC
A
and DAC
B
registers. Refer to
Figure 1-1 and Section 1.0 “Electrical Characteris-
tics” AC Electrical Characteristics table for detailed
input and output timing specifications for both Mode 0,0
and Mode 1,1 operation.
5.2 Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS
pin is then raised, causing the data to
be latched into the selected DAC’s input registers. The
MCP492X utilizes a double-buffered latch structure to
allow both DAC
A
’s and DAC
B
’s outputs to be
syncronized with the LDAC
pin, if desired. Upon the
LDAC
pin achieving a low state, the values held in the
DAC’s input registers are transferred into the DACs’
output registers. The outputs will transition to the value
and held in the DAC
X
register.
All writes to the MCP492X are 16-bit words. Any
clocks past 16 will be ignored. The most significant
four bits are configuration bits. The remaining 12 bits
are data bits. No data can be transferred into the
device with CS
high. This transfer will only occur if 16
clocks have been transferred into the device. If the ris-
ing edge of CS
occurs prior, shifting of data into the
input registers will be aborted.
REGISTER 5-1: WRITE COMMAND REGISTER
bit 15 A/B: DAC
A
or DAC
B
Select bit
1 = Write to DAC
B
0 = Write to DAC
A
bit 14 BUF: V
REF
Input Buffer Control bit
1 = Buffered
0 = Unbuffered
bit 13 GA
: Output Gain Select bit
1 =1x (V
OUT
= V
REF
* D/4096)
0 =2x (V
OUT
= 2 * V
REF
* D/4096)
bit 12 SHDN
: Output Power Down Control bit
1 = Output Power Down Control bit
0 = Output buffer disabled, Output is high impedance
bit 11-0 D11:D0: DAC Data bits
12 bit number “D” which sets the output value. Contains a value between 0 and 4095.
Upper Half:
W-x W-x W-x W-0 W-x W-x W-x W-x
A
/B BUF GA SHDN D11 D10 D9 D8
bit 15 bit 8
Lower Half:
W-x W-x W-x W-x W-x W-x W-x W-x
D7 D6 D5 D4
D3 D2 D1 D0
bit 7 bit 0
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown