MCP4921/4922 12-Bit DAC with SPI™ Interface Features Description • • • • • • • • • • • • • The Microchip Technology Inc. MCP492X are 2.7 – 5.5V, low-power, low DNL, 12-Bit Digital-to-Analog Converters (DACs) with optional 2x buffered output and SPI interface. The MCP492X are DACs that provide high accuracy and low noise performance for industrial applications where calibration or compensation of signals (such as temperature, pressure and humidity) are required.
MCP4921/4922 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VDD ............................................................................................................. 6.5V † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied.
MCP4921/4922 5V AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 kΩ to GND, CL = 100 pF TA = -40 to +85°C. Typical values at +25°C. Parameters Sym Min Typ Max Units Conditions Output Swing VOUT — — Phase Margin θm 0.010 to VDD – 0.040 — 66 — degrees Slew Rate SR — 0.55 — V/µs Short Circuit Current ISC — 15 24 mA tsettling — 4.
MCP4921/4922 3V AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 3V, AVSS = 0V, VREF = 2.048V external, output buffer gain (G) = 1x, RL = 5 kΩ to GND, CL = 100 pF TA = -40 to +85°C. Typical values at 25°C Parameters Sym Min Typ Max Units Input Capacitance – Unbuffered Mode CVREF — 7 — pF Multiplier Mode -3 dB Bandwidth fVREF — 440 — kHz VREF = 2.048V ±0.1 Vp-p, unbuffered, G=1 fVREF — 390 — kHz VREF = 2.048V ±0.
MCP4921/4922 5V EXTENDED TEMPERATURE SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 5V, AVSS = 0V, VREF = 2.048V, output buffer gain (G) = 2x, RL = 5 kΩ to GND, CL = 100 pF. Typical values at +125°C by characterization or simulation. Parameters Sym Min Typ Max Units gE — -0.10 — % of FSR ∆G/°C — -3 — ppm/°C Input Range - Buffered Mode VREF — 0.040 to VDD0.
MCP4921/4922 AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS) Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C. Typical values are at +25°C. Parameters Sym Min Typ Max Units Schmitt Trigger High-Level Input Voltage (All digital input pins) VIH 0.7 VDD — — V Schmitt Trigger Low-Level Input Voltage (All digital input pins) VIL — — 0.2 VD V Conditions D VHYS — 0.
MCP4921/4922 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, AVSS = GND.
MCP4921/4922 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
MCP4921/4922 5 4 3 2 1 0 -1 -2 -3 -4 -5 3 Ambient Temperature 125C 85 VREF 2 25 1 3 4 5.5 0 -1 -2 -3 -4 0 1024 2048 3072 4096 0 1024 Code (Decimal) FIGURE 2-6: Temperature. INL vs. Code and Ambient FIGURE 2-9: 2048 3072 Code (Decimal) 4096 INL vs. Code and VREF. 2 2.5 2 0 INL (LSB) Absolute INL (LSB) 2 1 INL (LSB) INL (LSB) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V , AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 1.5 1 -2 -4 0.
MCP4921/4922 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, AVSS = 0V, VREF = 2.048V, Gain = 2. 210 400 5.5V 5.5V 5.0V 4.0V 3.0V 2.7V 5.0V 4.0V 3.0V 2.7V 170 VDD 150 350 IDD (µA) 250 130 110 200 0 20 40 60 80 100 120 Ambient Temperature (°C) IDD (µA) MCP4921 IDD Histogram IDD (µA) 9 16 8 14 7 12 6 5 4 3 MCP4922 IDD Histogram FIGURE 2-15: (VDD = 2.7V).
MCP4921/4922 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V , AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 2 -0.08 VDD 5.5V 5.0V 4.0V 1 3.0V 2.7V 0.5 5.5V Gain Error (%) ISHDN (µA) 1.5 VDD -0.1 5.0V -0.12 4.0V 3.0V 2.7V -0.14 -0.16 0 -40 -20 -40 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-17: Hardware Shutdown Current vs. Ambient Temperature and VDD. -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-20: Gain Error vs.
MCP4921/4922 VDD 5.5V 5.0V 4.0V 3.0V 2.7V 0.0045 VOUT_LOW Limit (Y-AVSS)(V) 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 0.004 5.5V 0.0035 0.003 5.0V 0.0025 4.0V 3.0V 2.7V 0.002 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (ºC) 0 20 40 60 80 100 120 Ambient Temperature (ºC) FIGURE 2-23: Input Hysteresis vs. Ambient Temperature and VDD. FIGURE 2-26: VOUT Low Limit vs. Ambient Temperature and VDD. 18 175 VREF_UNBUFFERED Impedance (kOhm) 5.5V 2.7V VDD 170 165 160 VDD 17 5.5V 5.
MCP4921/4922 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V , AVSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 kΩ, CL = 100 pF. VOUT VOUT SCK LDAC LDAC Time (1 µs/div) FIGURE 2-29: VOUT Rise Time 100%. Time (1 µs/div) FIGURE 2-32: VOUT Rise Time 25% - 75% VOUT VOUT SCK SCK LDAC LDAC Time (1 µs/div) VOUT Fall Time. FIGURE 2-33: Shutdown. VOUT SCK LDAC Time (1 µs/div) FIGURE 2-31: VOUT Rise Time Exit Ripple Rejection (dB) FIGURE 2-30: Time (1 µs/div) VOUT Rise Time 50%.
MCP4921/4922 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V , AVSS = 0V, VREF = 2.50V, Gain = 2, RL = 5 kΩ, CL = 100 pF. 0 Attenuation (dB) -2 -4 -6 -8 -10 -12 100 Frequency (kHz) FIGURE 2-35: 160 416 672 928 1184 1440 1696 1952 2208 2464 2720 2976 3232 3488 3744 1,000 Multiplier Mode Bandwidth.
MCP4921/4922 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP4921 Pin No. MCP4922 Pin No. Symbol 1 1 VDD — 2 NC No Connection 2 3 CS Chip Select Input 3 4 SCK Serial Clock Input 4 5 SDI Serial Data Input — 6 NC No Connection — 7 NC No Connection 5 8 LDAC Syncronization input used to transfer DAC settings from serial latches to the output latches. 3.1 Function Positive Power Supply Input (2.7V to 5.
MCP4921/4922 4.0 GENERAL OVERVIEW The MCP492X devices are voltage output string DACs. These devices include input amplifiers, rail-to-rail output amplifiers, reference buffers, shutdown and resetmanagement circuitry. Serial communication conforms to the SPI protocol. The MCP492X operates from 2.7V to 5.5V supplies.
MCP4921/4922 4.1 4.1.1 Circuit Descriptions OUTPUT AMPLIFIERS The DACs’ outputs are buffered with a low-power, precision CMOS amplifier. This amplifier provides low offset voltage and low noise. The output stage enables the device to operate with output voltages close to the power supply rails. Refer to Section 1.0 “Electrical Characteristics” for range and load conditions. In addition to resistive load driving capability, the amplifier will also drive high capacitive loads without oscillation.
MCP4921/4922 5.0 SERIAL INTERFACE 5.1 Overview 5.2 The write command is initiated by driving the CS pin low, followed by clocking the four configuration bits and the 12 data bits into the SDI pin on the rising edge of SCK. The CS pin is then raised, causing the data to be latched into the selected DAC’s input registers. The MCP492X utilizes a double-buffered latch structure to allow both DACA’s and DACB’s outputs to be syncronized with the LDAC pin, if desired.
MCP4921/4922 CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK (mode 0,0) config bits SDI (mode 1,1) 12 data bits A/B BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LDAC VOUT FIGURE 5-1: Write Command. 2004 Microchip Technology Inc.
MCP4921/4922 At the time of this data sheet’s release, circuit examples had not completed testing. Your results may vary. VDD • • • • • Set Point or Offset Trimming Sensor Calibration Digitally-Controlled Multiplier/Divider Portable Instrumentation (Battery Powered) Motor Feedback Loop Control 6.1 Digital Interface The MCP492X utilizes a 3-wire syncronous serial protocol to transfer the DACs’ setup and output values from the digital source.
MCP4921/4922 6.4 6.4.1.1 Single-Supply Operation If the output range is reduced relative to AVSS, simply reducing VREF will reduce the magnitude of each output step. If the application is calibrating the threshold of a diode, transistor or resistor tied to AVSS or VREF, a theshold range of 0.8V may be desired to provide 200 µV resolution. Two common methods to achieve a 0.8V range is to either reduce VREF to 0.82V or use a voltage divider on the DAC’s output.
MCP4921/4922 6.4.1.2 Building a “Window” DAC If the threshold is not near VREF or AVSS, then creating a “window” around the threshold has several advantages. One simple method to create this “window” is to use a voltage divider network with a pull-up and pulldown resistor. Example 6-2 and Example 6-4 illustrates this concept. When calibrating a set point or threshold of a sensor, rarely does the sensor utilize the entire output range of the DAC.
MCP4921/4922 6.5 Bipolar Operation Example 6-3 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC's output to a selected offset. Note that R4 can be tied to VREF, instead of AVSS, if a higher offset is desired. Note that a pull-up to VREF could be used, instead of R4, if a higher offset is desired. Bipolar operation is achievable using the MCP492X by using an external operational amplifier (op amp).
MCP4921/4922 6.6 Selectable Gain and Offset Bipolar Voltage Output Using A Dual DAC This circuit is typically used in Multiplier mode and is ideal for linearizing a sensor whose slope and offset varies. Refer to Section 6.9 “Using Multiplier Mode” for more information on Multiplier mode. In some applications, precision digital control of the output range is desirable. Example 6-4 illustrates how to use the MCP4922 to achieve this in a bipolar or single-supply application.
MCP4921/4922 6.7 Designing A Double-Precision DAC Using A Dual DAC 1. Example 6-5 illustrates how to design a single-supply voltage output capable of up to 24-bit resolution from a dual 12-bit DAC. This design is simply a voltage divider with a buffered output. As an example, if a similar application to the one developed in Section 6.5.1 “Design a bipolar dac using Example 6-3” required a resolution of 1 µV instead of 1 mV and a range of 0V to 4.1V, then 12-bit resolution would not be adequate. 2. 3.
MCP4921/4922 6.8 Building A Programmable Current Source Example 6-6 illustrates a variation on a voltage follower design where a sense resistor is used to convert the DAC’s voltage output into a digitally-selectable current source. Adding the resistor network from Example 6-2 would be advantageous in this application. The smaller Rsense is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled with.
MCP4921/4922 7.0 DEVELOPMENT SUPPORT 7.1 Evaluation & Demonstration Boards The Mixed Signal PICtailTM Board supports the MCP492X family of devices. Please refer to www.microchip.com for further information on this products capabilities and availability. 2004 Microchip Technology Inc. 7.2 Application Notes and Tech Briefs Application notes illustrating the performace and implementation of the MCP492X are planned but currently not released. Please refer to www.microchip.com for further information.
MCP4921/4922 8.0 PACKAGING INFORMATION 8.1 Package Marking Information Example: 8-Lead MSOP XXXXXX 4921E YWWNNN 412256 8-Lead PDIP (300 mil) Example: XXXXXXXX XXXXXNNN YYWW MCP4921 E/P256 0412 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Legend: Note: * XX...
MCP4921/4922 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP4922) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP4922) XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP4922) XXXXXX YYWW NNN 2004 Microchip Technology Inc.
MCP4921/4922 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A2 A c φ A1 (F) L β Units Dimension Limits n p MIN INCHES NOM MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0° 0.08 0.22 5° 5° - MIN 8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness A1 .000 .006 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .
MCP4921/4922 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic § A A2 A1 E E1 D L c B1 B eB
MCP4921/4922 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .
MCP4921/4922 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .
MCP4921/4922 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .150 .337 .010 .
MCP4921/4922 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B1 α β MIN .033 .002 .246 .169 .193 .020 0 .004 .
MCP4921/4922 NOTES: DS21897A-page 36 2004 Microchip Technology Inc.
MCP4921/4922 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
MCP4921/4922 NOTES: DS21897A-page 38 2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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