Datasheet

MCP4802/4812/4822
DS22249A-page 6  2010 Microchip Technology Inc.
Output Amplifier
Output Swing V
OUT
— 0.01 to
V
DD
– 0.04
— V Accuracy is better than 1 LSb
for
V
OUT
= 10 mV to (V
DD
–
40 mV)
Phase Margin PM — 66 — Degree (°) C
L
= 400 pF, R
L
= 
Slew Rate SR — 0.55 — V/µs
Short Circuit Current I
SC
—17—mA
Settling Time t
SETTLING
— 4.5 — µs Within 1/2 LSb of final value
from 1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC-to-DAC Crosstalk — <10 — nV-s
Major Code Transition
Glitch
— 45 — nV-s 1 LSb change around major
carry (0111...1111 to
1000...0000)
Digital Feedthrough — <10 — nV-s
Analog Crosstalk — <10 — nV-s
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, V
DD
= 2.7V – 5.5V, T
A
= -40 to +125°C.
Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Schmitt Trigger High-Level
Input Voltage
(All digital input pins)
V
IH
0.7 V
DD
——V
Schmitt Trigger Low-Level
Input Voltage
(All digital input pins)
V
IL
——0.2V
DD
V
Hysteresis of Schmitt Trigger
Inputs
V
HYS
—0.05V
DD
—V
Input Leakage Current I
LEAKAGE
-1 — 1 ALDAC = CS = SDI = SCK =
V
DD
or V
SS
Digital Pin Capacitance
(All inputs/outputs)
C
IN
,
C
OUT
—10—pFV
DD
= 5.0V, T
A
= +25°C,
f
CLK
= 1 MHz (Note 1)
Clock Frequency F
CLK
——20MHzT
A
= +25°C (Note 1)
Clock High Time t
HI
15 — — ns Note 1
Clock Low Time t
LO
15 — — ns Note 1
CS
Fall to First Rising CLK
Edge
t
CSSR
40 — — ns Applies only when CS falls with
CLK high. (Note 1)
Data Input Setup Time t
SU
15 — — ns Note 1
Data Input Hold Time t
HD
10 — — ns Note 1
SCK Rise to CS Rise Hold
Time
t
CHS
15 — — ns Note 1
Note 1: This parameter is ensured by design and not 100% tested.
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, V
DD
= 5V, V
SS
= 0V, V
REF
= 2.048V, Output Buffer Gain (G) = 2x,
R
L
= 5 k to GND, C
L
= 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters Sym Min Typ Max Units Conditions
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.