Datasheet

 2010 Microchip Technology Inc. DS22249A-page 25
MCP4802/4812/4822
6.0 TYPICAL APPLICATIONS
The MCP4802/4812/4822 family of devices are
general purpose DACs for various applications where
a precision operation with low-power and internal
voltage reference is required.
Applications generally suited for the devices are:
• Set Point or Offset Trimming
• Sensor Calibration
• Precision Selectable Voltage Reference
• Portable Instrumentation (Battery-Powered)
• Calibration of Optical Communication Devices
6.1 Digital Interface
The MCP4802/4812/4822 devices utilize a 3-wire
synchronous serial protocol to transfer the DAC’s setup
and input codes from the digital devices. The serial
protocol can be interfaced to SPI or Microwire
peripherals that is common on many microcontroller
units (MCUs), including Microchip’s PIC
®
MCUs and
dsPIC
®
DSCs.
In addition to the three serial connections (CS
, SCK
and SDI), the LDAC
signal synchronizes the two DAC
outputs. By bringing down the LDAC
pin to “low”, all
DAC input codes and settings in the two DAC input reg-
isters are latched into their DAC output registers at the
same time. Therefore, both DAC
A
and DAC
B
outputs
are updated at the same time. Figure 6-1 shows an
example of the pin connections. Note that the LDAC
pin
can be tied low (V
SS
) to reduce the required
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16 clock transmission has been received and the CS
pin has been raised.
6.2 Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter out the noise in the power supply
traces. The noise can be induced onto the power
supply's traces from various events such as digital
switching or as a result of changes on the DAC's
output. The bypass capacitor helps to minimize the
effect of these noise sources. Figure 6-1 illustrates an
appropriate bypass strategy. In this example, two
bypass capacitors are used in parallel: (a) 0.1 µF
(ceramic) and (b)10 µF (tantalum). These capacitors
should be placed as close to the device power pin
(V
DD
) as possible (within 4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V
DD
and
V
SS
of the device should reside on the analog plane.
6.3 Output Noise Considerations
The voltage noise density (in µV/Hz) is illustrated in
Figure 2-13. This noise appears at V
OUTX
, and is
primarily a result of the internal reference voltage.
Its 1/f corner (f
CORNER
) is approximately 400 Hz.
Figure 2-14 illustrates the voltage noise (in mV
RMS
or
mV
P-P
). A small bypass capacitor on V
OUTX
is an
effective method to produce a single-pole Low-Pass
Filter (LPF) that will reduce this noise. For instance, a
bypass capacitor sized to produce a 1 kHz LPF would
result in an E
NREF
of about 100 µV
RMS
. This would be
necessary when trying to achieve the low DNL error
performance (at G = 1) that the MCP4802/4812/4822
devices are capable of. The tested range for stability is
.001µF through 4.7 µF.
FIGURE 6-1: Typical Connection
Diagram.
6.4 Layout Considerations
Inductively-coupled AC transients and digital switching
noises can degrade the output signal integrity, and
potentially reduce the device performance. Careful
board layout will minimize these effects and increase
the Signal-to-Noise Ratio (SNR). Bench testing has
shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs and
isolated outputs with proper decoupling, is critical for
the best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
V
DD
V
DD
V
DD
AV
SS
AV
SS
V
SS
V
OUTA
V
OUTB
PIC
®
Microcontroller
V
OUTA
V
OUTB
SDI
SDI
CS
1
SDO
SCK
LDAC
CS
0
1µF
1µF
MCP48x2
MCP48x2
C1 = 10 µF
C2 = 0.1 µF
C1
C2
C2
C1
C1
C2