Datasheet
2012-2013 Microchip Technology Inc. DS20002286B-page 63
MCP3911
7.8 GAINCAL_CHn Registers - Digital
Gain Error Calibration Registers
7.9 VREFCAL Register – Internal
Voltage Reference Temperature
Coefficient Adjustment Register
This register is only for advanced users. This register
should not be written unless the user wants to calibrate
the temperature coefficient of the whole system or
application. The default value of this register is set to
0x42.
Name Bits Address Cof
GAINCAL_CH0 24
0x11
R/W
GAINCAL_CH1 24
0x17
R/W
REGISTER 7-8: GAINCAL_CHn REGISTER
R/W-0 R/W-0 R/W-0 ... R/W-0 R/W-0 R/W-0 R/W-0
GAIN-
CAL_CHn<23>
GAIN-
CAL_CHn<22>
GAIN-
CAL_CHn<21>
... GAIN-
CAL_CHn<3>
GAIN-
CAL_CHn<2>
GAIN-
CAL_CHn<1>
GAIN-
CAL_CHn<0>
bit 23 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-0 Digital gain error calibration value for the corresponding Channel CHn. This register is 24-bit signed
MSB first coding with a range of -1x to +0.9999999x (from 0x80000 to 0x7FFFFF). The gain calibration
adds 1x to this register and multiplies it to the output code of the channel bit by bit, after the offset
calibration. Thus, the range of the gain calibration is from 0x to 1.9999999x (from 0x80000 to
0x7FFFFF). The LSB corresponds to a 2
-23
increment in the multiplier.
CHn Output Code = (GAINCAL_CHn+1) x ADC CHn Output Code. This register is a “Don't Care” if
EN_GAINCAL = 0 (Offset calibration disabled), but its value is not cleared by the EN_GAINCAL bit.
Name Bits Address Cof
VREFCAL 8
0x1A
R/W
REGISTER 7-9: VREFCAL REGISTER
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0
VREFCAL<7> VREFCAL<6> VREFCAL<5> VREFCAL<4> VREFCAL<3> VREFCAL<2> VREFCAL<1> VREFCAL<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 Internal Voltage Temperature coefficient register value (see Section 5.7.3 “Temperature
compensation (VREFCAL register)” for complete description).