Datasheet

MCP3911

DS20002286B-page 60  2012-2013 Microchip Technology Inc.

bit 5 WRITE: Address Loop Setting for Write mode

1 = Address counter loops on entire register map (DEFAULT)

0 = Address not incremented, continually write same single register

bit 4-3 WIDTH<1:0> ADC Channel output data word width

11 = Both channels are in 24-bit mode(DEFAULT)

10 = Channel1 in 16-bit mode, Channel0 in 24-bit mode

01 = Channel1 in 16-bit mode, Channel0 in 24-bit mode

00 = Both channels are in 16-bit mode

bit 2 EN_OFFCAL Enables or disables the 24-bit digital offset calibration on both channels

1 = Enabled; this mode does not add any group delay

0 = Disabled (DEFAULT)

bit 1 EN_GAINCAL Enables or disables the 24-bit digital offset calibration on both channels

1 = Enabled; this mode adds a group delay on both channels of 24 DMCLK periods. All data ready

pulses are delayed by 24 clock periods compared to the mode with EN_GAINCAL = 0

0 = Disabled (DEFAULT)

bit 0 Unimplemented: Read as ‘0’