Datasheet

 2012-2013 Microchip Technology Inc. DS20002286B-page 57
MCP3911
7.3 PHASE Register –
Phase Configuration Register
Any write to one of these two addresses (0x07 and
0x08) creates an internal reset and restart sequence.
Name Bits Address Cof
PHASE 16 0x07 R/W
REGISTER 7-3: PHASE REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — PHASE<11> PHASE<10> PHASE<9> PHASE<8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASE<7> PHASE<6> PHASE<5> PHASE<4> PHASE<3> PHASE<2> PHASE<1> PHASE<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-0 CH0 relative to CH1 Phase Delay:
PHASE<11:0>: CH0 Relative to CH1 Phase Delay bits.
Delay = PHASE Register’s two’s complement code/DMCLK (Default PHASE = 0).