Datasheet

 2012-2013 Microchip Technology Inc. DS20002286B-page 49
MCP3911
6.10.1 DATA READY PIN (DR) CONTROL
USING DRMODE BITS
There are four modes that control the data ready
pulses and these modes are set with the
DRMODE<1:0> bits in the STATUSCOM register. For
power metering applications, DRMODE<1:0> = 00 is
recommended (Default mode).
The position of the data ready pulses vary, with respect
to this mode, to the OSR and to the PHASE settings:
• DRMODE<1:0> = 11: Both data ready pulses
from ADC Channel 0 and ADC Channel 1 are
output on the DR
pin.
• DRMODE<1:0> = 10: Data ready pulses from
ADC Channel 1 are output on the DR
pin. The
data ready pulse from ADC Channel 0 is not
present on the pin.
• DRMODE<1:0> = 01: Data ready pulses from
ADC Channel 0 are output on the DR
pin. The
data ready pulse from ADC Channel 1 is not
present on the pin.
• DRMODE<1:0> = 00 (Recommended and
Default mode): Data ready pulses from the
lagging ADC between the two are output on the
DR
pin. The lagging ADC depends on the PHASE
register and on the OSR. In this mode, the two
ADCs are linked so their data is latched together
when the lagging ADC output is ready.
6.10.2 ADC CHANNELS LATCHING AND
SYNCHRONIZATION
The ADC channels data output registers (addresses
0x00 to 0x05) have a double buffer output structure.
The two sets of latches in series are triggered by the
data ready signal and an internal signal indicating the
beginning of a read communication sequence (read
start).
The first set of latches holds each ADC channel data
output register when the data is ready and latches both
outputs together when DRMODE<1:0> = 00. This
behavior is synchronous with the MCLK.
The second set of latches ensures that when reading
starts on an ADC output, the corresponding data is
latched so that no data corruption can occur within a
read. This behavior is synchronous with the SCK clock.
If an ADC read has started, to read the following ADC
output, the current reading needs to be fully completed
(all bits must be read on the SDO pin from the ADC
output data registers).
Since the double output buffer structure is triggered
with two events that depend on two asynchronous
clocks (data ready with MCLK and read start with SCK),
it is recommended to synchronize the reading of the
channels with the MCU or processor using one of the
following methods:
1. Use the data ready pin pulses as an interrupt
– Once a falling edge occurs on the DR
pin, the
data is available for reading on the ADC output
registers after the t
DODR
timing. If this timing is
not respected, data corruption can occur.
2. Use a timer clocked with MCLK as a
synchronization event – Since the data ready
is synchronous with MCLK, the user can
calculate the position of the data ready
depending on the PHASE<11:0>, the
OSR<2:0> and the PRE<1:0> settings for each
channel. Here, the t
DODR
timing needs to be
added to this calculation to avoid data
corruption.
3. Poll the DRSTATUS<1:0> bits in the
STATUSCOM register – This method consists
of reading continuously the STATUSCOM
register and waits for the DRSTATUS bits to be
equal to ‘0’. When this event happens, the user
can start a new communication to read the
desired ADC data. In this case, no additional
timing is required.
The first method is the preferred method as it can be
used without adding additional MCU code space, but it
requires connecting the DR
pin to an I/O pin of the
microcontroller. The other two methods require more
MCU code space and execution time, but they allow
synchronizing the reading of the channels without
connecting the DR
pin, which saves one I/O pin on the
MCU.
6.10.3 DATA READY PULSES WITH
SHUTDOWN OR RESET
CONDITIONS
There are no data ready pulses if DRMODE<1:0> = 00
when either one or both of the ADCs are in Reset or
Shutdown mode. In Mode 0,0, a data ready pulse only
happens when both ADCs are ready. Any data ready
pulse corresponds to one data on both ADCs. The two
ADCs are linked together and act as if there was only
one channel with the combined data of both ADCs.
This mode is very practical when both ADC channels’
data retrieval and processing need to be synchronized,
as in power metering applications.
Note: If DRMODE<1:0> = 11, the user is still
able to retrieve the data ready pulse for
the ADC not in Shutdown or Reset mode
(i.e., only 1 ADC channel needs to be
awake).