Datasheet

MCP3911
DS20002286B-page 48  2012-2013 Microchip Technology Inc.
FIGURE 6-8: Recommended Configuration Sequence at Power-up.
6.9 Data Ready Pin (DR)
To signify when channel data is ready for transmission,
the data ready signal is available on the Data Ready pin
(DR) through an active-low pulse at the end of a
channel conversion.
The data ready pin outputs an active-low pulse with a
period that is equal to the DRCLK period and a width
equal to one DMCLK period.
When not active-low, this pin can either be in high-
impedance (when DR_HIZ
= 0) or in a defined logic
high state (when DR_HIZ = 1). This is controlled
through the STATUSCOM register. This allows multiple
devices to share the same data ready pin (with a
pull-up resistor connected between DR
and DV
DD
) in
3-phase energy meter designs to reduce pin count. A
single device on the bus does not require a pull-up
resistor and therefore it is recommended to use
DR_HIZ
= 1 configuration for such applications.
After a data ready pulse has occurred, the ADC output
data can be read through SPI communication. Two sets
of latches at the output of the ADC prevent the
communication from outputting corrupted data (see
Section 6.10 “ADC Data Latches and Data Ready
Modes (DRMODE<1:0>)”).
The CS
pin has no effect on the DR pin, which means
even if CS
is logic high, data ready pulses will be
provided (except when the configuration prevents them
from outputting data ready pulses). The DR
pin can be
used as an interrupt when connected to an MCU or a
DSP. While the RESET
pin is logic low, the DR pin is
not active.
6.10 ADC Data Latches and Data Ready
Modes (DRMODE<1:0>)
To ensure that both channels’ ADC data is present at
the same time for SPI read, regardless of phase delay
settings for either or both channels, there are two sets
of ADC data latches in series with both the data ready
and the ‘read start’ triggers.
The first set of latches holds each output when the data
is ready and latches both outputs together when
DRMODE<1:0> = 00. When this mode is on, both
ADCs work together and produce one set of available
data after each data ready pulse (that corresponds to
the lagging ADC data ready). The second set of latches
ensures that when reading starts on an ADC output, the
corresponding data is latched so that no data
corruption can occur.
If an ADC read has started, to read the following ADC
output, the current reading needs to be completed (all
bits must be read from the ADC Output Data registers).
00011010
CS
SCK
SDI
AV
DD
, DV
DD
11XXXXXX
CONFIG2
ADDR/W
CONFIG2
Optional RESET of both ADCs One command for writing complete configuration (without calibration)
PHASE ADDR/W GAIN STATUSCOM CONFIGPHASE
00001110 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx