Datasheet

 2012-2013 Microchip Technology Inc. DS20002286B-page 47
MCP3911
FIGURE 6-7: Typical Continuous Read Communication (SPI Mode 1,1).
6.7.2 CONTINUOUS WRITE
Both ADCs are powered up with their default
configurations and begin to output data ready pulses
immediately (RESET<1:0> and SHUTDOWN<1:0>
bits are off by default).
The default output codes for both ADCs are all zeros.
The default modulator output for both ADCs is ‘0011’
(corresponding to a theoretical zero voltage at the
inputs). The default phase is zero between the two
channels.
It is recommended to enter into ADC Reset mode for
both ADCs, just after power-up. It is because the
desired MCP3911 register configuration may not be the
default one. In this case, the ADC outputs undesired
data. Within the ADC Reset mode (RESET<1:0> = 11),
the user can configure the whole part with a single
communication. The write commands automatically
increment the address so that the user can start writing
the PHASE register and finish with the CONFIG
register in only one communication (see Figure 6-8).
The RESET<1:0> bits are in the last byte of the
CONFIG register to allow exiting the Soft Reset mode,
and have the whole part configured and ready to run in
only one command.
6.7.3 REGISTER GROUPS AND TYPES
The following register sets are defined as groups:
The following register sets are defined as types:
6.8 Situations that Reset ADC Data
Immediately after the following actions, the ADCs are
reset and automatically restarted to provide proper
operation:
1. Change in PHASE register
2. Change in the OSR setting
3. Change in the PRESCALE setting
4. Overwrite of the same PHASE register value
5. Change in the CLKEXT setting
6. Change in the VREFEXT setting
7. Change in the MODOUT setting
After these temporary resets, the ADCs go back to
normal operation without the need for an additional
command. If the same value is written in the PHASE
register, it can be used to serially Soft Reset the ADCs,
without using the RESET bits in the Configuration
register.
CH0 ADC
ADDR/R
CS
SCK
SDI
CH0 ADC
Upper byte
SDO
CH0 ADC
Middle byte
CH0 ADC
Lower byte
DR
CH1 ADC
Upper byte
CH1 ADC
Middle byte
CH1 ADC Lower byte
CH0 ADC
Upper byte
CH0 ADC
Middle byte
CH0 ADC
Lower byte
CH1 ADC
Upper byte
CH1 ADC
Middle byte
CH1 ADC Lower byte
These bytes are not present when WIDTH=0 (16-bit mode)
HiZ
TABLE 6-1: REGISTER GROUPS
Group Addresses
ADC DATA CH0 0x00-0x02
ADC DATA CH1 0x03-0x05
MOD, PHASE, GAIN 0x06-0x09
CONFIG, STATUSCOM 0x0A-0x0D
OFFCAL_CH0, GAINCAL_CH0 0x0E-0x13
OFFCAL_CH1, GAINCAL_CH1 0x14-0x19
VREFCAL 0x1A
TABLE 6-2: REGISTER TYPES
Type Addresses
ADC DATA (both channels) 0x00-0x05
CONFIGURATION 0x06-0x1A