Datasheet

MCP3911
DS20002286B-page 40  2012-2013 Microchip Technology Inc.
5.11 Crystal Oscillator
The MCP3911 includes a Pierce-type crystal oscillator
with very high stability and ensures very low tempco
and jitter for the clock generation. This oscillator can
handle up to 20 MHz crystal frequencies, provided that
proper load capacitances and quartz quality factor are
used.
For a proper start-up, the load capacitors of the crystal
should be connected between OSC1 and D
GND
and
between OSC2 and D
GND
. They should also respect
the following equation:
EQUATION 5-7:
When CLKEXT = 1, the crystal oscillator is bypassed
by a digital buffer to allow direct clock input for an
external clock (see Figure 4-1).
When CLKEXT = 1, it is recommended to connect
OSC2 pin to D
GND
directly at all times. The external
clock should not be higher than 20 MHz before
prescaler (MCLK < 20 MHz) for proper operation.
5.12 Digital System Offset and Gain
Errors
The MCP3911 incorporates two sets of additional
registers per channel to perform system digital offset
and gain errors calibration. If the calibration is enabled,
each channel has its own set of registers associated
that will modify the output result of the channel. The
gain and offset calibrations can be enabled or disabled
through two configuration bits (EN_OFFCAL and
EN_GAINCAL). These two bits enable or disable
system calibration on both channels at the same time.
When both calibrations are enabled, the output of the
ADC is modified in Equation 5-8:
EQUATION 5-8: DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS
CALCULATIONS
TABLE 5-9: PHASE VALUES WITH
MCLK = 4 MHZ, OSR = 4096
Phase Register Value Hex
Delay
(CH0 relative
to CH1)
011111111111 0x7FF + 2047 µs
011111111110 0x7FE + 2046 µs
000000000001 0x001 + 1 µs
000000000000 0x000 0 µs
111111111111 0xFFF - 1 µs
100000000001 0x801 - 2047 µs
100000000000 0x800 -2048 µs
R
M
1.6 10
6
×
1
fC
•
LOAD
------------------------


×
2
<
Where:
f = crystal frequency in MHz
C
LOAD
= load capacitance in pF including
parasitics from the PCB
R
M
= motional resistance in ohms of the
quartz
Note: In addition to the conditions defining the
maximum MCLK input frequency range,
the AMCLK frequency should be
maintained inferior to the maximum limits
defined in Ta bl e 5 -2 to ensure the
accuracy of the ADCs. If these limits are
exceeded, it is recommended to either
choose a larger OSR or a large prescaler
value, so that AMCLK can respect these
limits.
DATA_CHn post cal–()DATA_CHn pre cal–()OFFCAL_CHn+()1GAINCAL_CHn+() × =