Datasheet

MCP3911
DS20002286B-page 38  2012-2013 Microchip Technology Inc.
5.7.3 TEMPERATURE COMPENSATION
(VREFCAL REGISTER)
The internal voltage reference comprises a proprietary
circuit and algorithm to compensate first order and
second order temperature coefficients. The
compensation allows very low temperature coefficients
(typically 7 ppm/°C) on the entire range of temperatures
from -40°C to +125°C. This temperature coefficient varies
from part to part.
This temperature coefficient can be adjusted on each
part through the VREFCAL register (address 0x1A).
This register is only for advanced users. This register
should not be written unless the user wants to calibrate
the temperature coefficient of the whole system or
application. The default value of this register is set to
0x42. The typical variation of the temperature
coefficient of the internal voltage reference, with
respect to VREFCAL register code, is shown in
Figure 5-6. Modifying the value stored in the VREFCAL
register may also vary the output voltage, in addition to
the temperature coefficient.
FIGURE 5-6: V
REF
Tempco vs. VREFCAL
Trimcode Chart.
5.8 Power-on Reset
The MCP3911 contains an internal POR circuit that
monitors both analog and digital supply voltages
during
operation. The typical threshold for a power-up event
detection is 2.1V ±5% and a typical start-up time (t
POR
)
of 50 µs. The POR circuit has a built-in hysteresis for
improved transient spikes immunity that has a typical
value of 200 mV. Proper decoupling capacitors (0.1 µF
ceramic and 10 µF in parallel are sufficient in most
cases) should be mounted as close as possible to the
AV
DD
and DV
DD
pins, providing additional transient
immunity.
Figure 5-7 illustrates the different conditions at
power-up and a power-down event in typical
conditions. All internal DC biases are not settled until at
least 1 ms, in worst case conditions, after system POR.
Any data ready pulse that occurs within 1 ms, plus the
sinc filter settling time after system reset, should be
ignored to ensure proper accuracy. After POR, data
ready pulses are present at the pin with all the default
conditions in the configuration registers.
Both AV
DD
and DV
DD
are monitored so either power
supply can sequence first.
FIGURE 5-7: Power-on Reset Operation.
0
10
20
30
40
50
60
0 64 128 192
256
V
REF
Drift (ppm)
VREFCAL Register Trim Code (decimal)
POR
State
Power-Up
Normal
POR
State
Biases are
unsettled.
Conversions
started here may
not be accurate.
Biases are settled.
Conversions started
here are accurate.
Analog biases
settling time
SINC filter
settling
time
Voltage
(AV
DD
, DV
DD
)
Time
POR Threshold
up (2.1V typical)
(1.9V typical)
t
POR
Operation
Any data read pulse
occuring during this time
can yield inaccurate output
data. It is recommended to
discard them.