Datasheet
MCP3911
DS20002286B-page 36 2012-2013 Microchip Technology Inc.
5.6 ADC Output Coding
The second order modulator, SINC
3
+SINC
1
filter, PGA,
V
REF
and analog input structure, all work together to
produce the device transfer function for the analog to
digital conversion (see Equation 5-3).
The channel data is either a 16-bit or 24-bit word,
presented in 23-bit or 15-bit plus sign, two’s
complement format and is Most Significant Byte (MSB)
(left) justified.
The ADC data is two or three bytes wide depending on
the WIDTH<1:0> bits. The 16-bit mode includes a
round to the closest 16-bit word (instead of truncation),
to improve the accuracy of the ADC data.
In case of positive saturation (CHn+ – CHn- > V
REF
/
1.5), the output is locked to 7FFFFF for 24-bit mode
(7FFF for 16-bit mode). In case of negative saturation
(CHn+ – CHn- < -V
REF
/1.5), the output code is locked
to 800000 for 24-bit mode (8000 for 16-bit mode).
Equation 5-3 is only true for DC inputs. For AC inputs,
this transfer function needs to be multiplied by the
transfer function of the SINC
3
+SINC
1
filter (see
Equation 5-1 and Equation 5-3).
EQUATION 5-3:
The ADC resolution is a function of the OSR
(Section 5.5 “SINC3 + SINC1 Filter”). The resolution
is the same for both channels. No matter what the
resolution is, the ADC output data is always presented
in 24-bit words, with added zeros at the end, if the OSR
is not large enough to produce 24-bit resolution (left
justification).
DATA_CHn
CH
n+
CH
n-
–()
V
REF+
V
REF-
–
-----------------------------------------
8,388,608 G 1.5
×××
=
DATA_CHn
CH
n+
CH
n-
–()
V
REF+
V
REF-
–
-----------------------------------------
32 768,G1.5
×××
=
(For 24-bit Mode Or WIDTH = 1)
(For 16-bit Mode Or WIDTH = 0)
TABLE 5-5: OSR = 256 (AND HIGHER) OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal
Decimal
24-bit Resolution
0111 1111 1111 1111 1111 1111 0x7FFFFF + 8,388,607
0111 1111 1111 1111 1111 1110 0x7FFFFE + 8,388,606
0000 0000 0000 0000 0000 0000 0x000000 0
1111 1111 1111 1111 1111 1111 0xFFFFFF -1
1000 0000 0000 0000 0000 0001 0x800001 - 8,388,607
1000 0000 0000 0000 0000 0000 0x800000 - 8,388,608
TABLE 5-6: OSR = 128 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal
Decimal
23-bit Resolution
0111 1111 1111 1111 1111 111
0 0x7FFFFE + 4,194,303
0111 1111 1111 1110 1111 110
0 0x7FFFFC + 4,194,302
0000 0000 0000 0000 0000 000
0 0x000000 0
1111 1111 1111 1111 1111 111
0 0xFFFFFE -1
1000 0000 0000 0000 0000 001
0 0x800002 - 4,194,303
1000 0000 0000 0000 0000 000
0 0x800000 - 4,194,304
TABLE 5-7: OSR = 64 OUTPUT CODE EXAMPLES
ADC Output code (MSB First) Hexadecimal
Decimal
20-bit Resolution
0111 1111 1111 1111 1111 0 0 0 0 0x7FFFF0 + 524, 287
0111 1111 1111 1111 1110
0 0 0 0 0x7FFFE0 + 524, 286
0000 0000 0000 0000 0000
0 0 0 0 0x000000 0
1111 1111 1111 1111 1111
0 0 0 0 0xFFFFF0 -1
1000 0000 0000 0000 0001
0 0 0 0 0x800010 - 524, 287
1000 0000 0000 0000 0000
0 0 0 0 0x800000 - 524, 288