Datasheet

 2012-2013 Microchip Technology Inc. DS20002286B-page 35
MCP3911
The SINC
1
filter following the SINC
3
filter is only
enabled for the high OSR settings. This SINC
1
filter
provides additional rejection at a low cost with little
modification to the -3 dB bandwidth. For 24-Bit Output
mode (WIDTH = 1), the output of the sinc filter is
padded on the right with least significant zeros, up to
24 bits, for any resolution less than 24 bits. For 16-Bit
Output modes, the output of the sinc filter is rounded to
the closest 16-bit number, to conserve only 16-bit
words and to minimize truncation error.
The gain of the transfer function of this filter is 1 at each
multiple of DMCLK (typically 1 MHz), so a proper anti-
aliasing filter must be placed at the inputs. This
attenuates the frequency content around DMCLK and
keep the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple, first-
order RC network with a sufficiently low-time constant
to generate high rejection at DMCLK frequency
.
Any unsettled data is automatically discarded to avoid
data corruption. Each data ready pulse corresponds to
fully settled data at the output of the decimation filter.
The first data available at the output of the decimation
filter is present after the complete settling time of the
filter (see Table 5-4). After the first data has been
processed, the delay between two data ready pulses is
1/DRCLK. The data stream from input to output is
delayed by an amount equal to the settling time of the
filter (which is the group delay of the filter).
The achievable resolution, the -3 dB bandwidth and the
settling time at the output of the decimation filter (the
output of the ADC), is dependent on the OSR of each
sinc filter and is summarized in Tab le 5-4:
FIGURE 5-4: SINC Filter Frequency
Response, OSR = 256, MCLK = 4 MHz,
PRE<1:0> =
00.
FIGURE 5-5: SINC Filter Frequency
Response, OSR = 4096 (pink), OSR = 512
(blue), MCLK = 4 MHz, PRE<1:0> = 00.
TABLE 5-4: OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME
OSR<2:0> OSR
3
OSR
1
Total OSR Resolution In Bits
(No Missing Codes)
Settling Time -3 dB Bandwidth
000 32 1 32 17 96/DMCLK 0.26*DRCLK
001 64 1 64 20 192/DMCLK 0.26*DRCLK
010 128 1 128 23 384/DMCLK 0.26*DRCLK
011 256 1 256 24 768/DMCLK 0.26*DRCLK
100 512 1 512 24 1536/DMCLK 0.26*DRCLK
101 512 2 1024 24 2048/DMCLK 0.37*DRCLK
110 512 4 2048 24 3072/DMCLK 0.42*DRCLK
111 512 8 4096 24 5120/DMCLK 0.43*DRCLK
-120
-100
-80
-60
-40
-20
0
1 10 100 1000 10000 100000
Magnitude (dB)
Input Frequency (Hz)
-160
-140
-120
-100
-80
-60
-40
-20
0
1 100 10000 1000000
Magnitude (dB)
Input Frequency (Hz)