Datasheet

MCP3911
DS20002286B-page 34  2012-2013 Microchip Technology Inc.
FIGURE 5-2: MDAT Serial Outputs in
Function of the Modulator Output Code.
Since the Reset and Shutdown SPI commands are
asynchronous, the MDAT pins are resynchronized with
DMCLK after each time the part goes out of Reset and
Shutdown.
This means that the first output of MDAT, after a Soft
Reset or a Shutdown, is always 0011 after the first
DMCLK rising edge.
The two MDAT output pins are in high-impedance if the
RESET
pin is low.
5.5 SINC
3
+ SINC
1
Filter
The decimation filter present in both channels of the
MCP3911 is a cascade of two sinc filters (sinc
3
+sinc
1
):
a third order sinc filter with a decimation ratio of OSR
3
followed by first order sinc filter with a decimation ratio
of OSR
1
(moving average of OSR
1
values). Figure 5-3
represents the decimation filter architecture.
FIGURE 5-3: MCP3911 Decimation Filter Block Diagram.
Equation 5-1 contains the formula for calculating the
transfer function of the digital decimation filter and
settling time of the ADC:
EQUATION 5-1: SINC FILTER TRANSFER
FUNCTION
EQUATION 5-2: SETTING TIME OF THE
ADC AS A FUNCTION OF
DMCLK PERIODS
DMCLK
MDAT+2
MDAT+1
MDAT+0
MDAT-1
MDAT-2
COMP
AMCLK
<3>
COMP
<2>
COMP
<1>
COMP
<0>
Modulator
Output
SINC
3
SINC
1
Decimation
Filter Output
OSR
3
OSR
1
4
16 (WIDTH=0)
24 (WIDTH=1)
Decimation Filter
OSR
1
=1
Hz()
1z
- OSR
3
–


3
OSR
3
1z
1–
–()()
3
----------------------------------------------
1z
- OSR
1
OSR
3
×
–


OSR
1
1z
- OSR
3
–


×
---------------------------------------------------------
× =
Where zEXP2
π jf
in
⋅⋅ DMCLK ⁄ ()=
SettlingTime DMCLKPeriods()3OSR
3
× OSR
1
1–()OSR
3
× +=