Datasheet

 2012-2013 Microchip Technology Inc. DS20002286B-page 31
MCP3911
5.0 DEVICE OVERVIEW
5.1 Analog Inputs (CHn+/-)
The MCP3911 analog inputs can be connected directly
to current and voltage transducers (such as shunts,
current transformers or Rogowski coils). Each input pin
is protected by specialized ESD structures that are
certified to pass 4.0 kV HBM and 300V MM contact
charge. These structures allow bipolar ±2V continuous
voltage with respect to A
GND
to be present at their
inputs without the risk of permanent damage.
Both channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each
pin relative to A
GND
should be maintained in the ±1V
range during operation to ensure the specified ADC
accuracy. The common-mode signals should be
adapted to respect both the previous conditions and
the differential input voltage range. For best
performance, the common-mode signals should be
maintained to A
GND
.
5.2 Programmable Gain Amplifiers
(PGA)
The two Programmable Gain Amplifiers (PGAs) reside
at the front-end of each Delta-Sigma ADC. They have
two functions: translate the common-mode of the input
from A
GND
to an internal level between A
GND
and
A
VDD
, and amplify the input differential signal. The
translation of the common mode does not change the
differential signal, but recenters the common-mode so
that the input signal can be properly amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma
modulator must not be exceeded. The PGA is
controlled by the PGA_CHn<2:0> bits in the GAIN
register. The following table represents the gain
settings for the PGA:
5.3 Delta-Sigma Modulator
5.3.1 ARCHITECTURE
Both ADCs are identical in the MCP3911 and they
include a proprietary second-order modulator with a
multi-bit five-level DAC architecture (see Figure 5-1).
The quantizer is a flash ADC composed of four
comparators with equally spaced thresholds and a
thermometer output coding. The proprietary five-level
architecture ensures minimum quantization noise at
the outputs of the modulators without disturbing
linearity or inducing additional distortion. The sampling
frequency is DMCLK (typically 1 MHz with
MCLK = 4 MHz), so the modulator outputs are
refreshed at a DMCLK rate. The modulator outputs are
available in the MOD register or serially transferred on
each MDAT pin.
Figure 5-1 represents a simplified block diagram of the
Delta-Sigma ADC present on MCP3911.
FIGURE 5-1: Simplified Delta-Sigma ADC
Block Diagram.
Note: If the analog inputs are held to a potential
of -0.6 to -1V for extended periods of time,
MCLK must be present inside the device
to avoid large leakage currents at the
analog inputs. This is true even during the
Hard or Soft Reset mode of both ADCs.
However, during the Shutdown mode of
the two ADCs or POR state, the clock is
not distributed inside the circuit. During
these states, it is recommended to keep
the analog input voltages above -0.6V
referred to A
GND
to avoid high analog
inputs leakage currents.
TABLE 5-1: PGA CONFIGURATION
SETTING
Gain
PGA_CHn<2:0>
Gain
(V/V)
Gain
(dB)
V
IN
Range
(V)
000 10±0.6
001 26±0.3
010 4 12 ±0.15
011 8 18 ±0.075
10016 24 ±0.0375
10132 30 ±0.01875
Note: This table is defined with V
REF
= 1.2V. The
two undefined settings, 110 and 111 are
G=1.
Second-
Order
Integrator
Loop
Filter
Quantizer
DAC
Differential
Voltage Input
Output
Bitstream
five-level
Flash ADC
MCP3911 Delta-Sigma Modulator