Datasheet

 2012-2013 Microchip Technology Inc. DS20002286B-page 29
MCP3911
When an ADC exits ADC Shutdown mode, any phase
delay present before shutdown was entered is still
present. If one ADC was not in Shutdown mode, the
ADC exiting Shutdown mode automatically
resynchronizes the phase delay relative to the other
ADC channel, per the phase delay register block and
give data ready pulses accordingly.
If an ADC is placed in Shutdown mode while the other
is converting, the internal clock is not shut down. When
exiting Shutdown mode, the ADC is automatically
resynchronized with the clock that did not stop during
Reset.
If both ADCs are in Shutdown mode, the clock is no
longer distributed to the input structure or to the digital
core for low power operation. If the input voltage is
highly negative (typically below -0.6V, referred to
A
GND
), this can cause potential high analog input
leakage currents at the analog inputs. Once any of the
ADC is back to normal operation, the clock is
automatically distributed again.
4.22 Full Shutdown Mode
The lowest power consumption can be achieved when
SHUTDOWN<1:0> = 11, VREFEXT = CLKEXT = 1.
This mode is called Full Shutdown mode, and no
analog circuitry is enabled. In this mode, both AV
DD
and DV
DD
POR monitoring are also disabled. No clock
is propagated throughout the chip. Both ADCs are in
Shutdown, and the internal voltage reference is
disabled.
The clock is not distributed to the input structure any
longer. This can cause potential high analog inputs
leakage currents at the analog inputs, if the input
voltage is highly negative (typically below -0.6V,
referred to A
GND
).
The only circuit that remains active is the SPI interface,
but this circuit does not induce any static power
consumption. If SCK is idle, the only current
consumption comes from the leakage currents induced
by the transistors and is less than 1 µA on each power
supply.
This mode can be used to power down the chip
completely and avoid power consumption when there
is no data to convert at the analog inputs. Any SCK or
MCLK edge coming while in this mode induces
dynamic power consumption.
Once any of the SHUTDOWN, CLKEXT and VREFEXT
bits return to ‘0’, the two POR monitoring blocks are
back to operation, and AV
DD
and DV
DD
monitoring can
take place.
When exiting full Shutdown mode, the device resets to
its default configuration state. The Configuration bits all
reset to their default value, and the ADCs reset to their
initial state, requiring three DRCLK periods for an initial
data ready pulse. Exiting full Shutdown mode is
effectively identical to an internal reset or returning
from a POR condition.