Datasheet

MCP3911
DS20002286B-page 28  2012-2013 Microchip Technology Inc.
4.19 ADC Reset Mode
ADC Reset mode (also called Soft Reset mode) can
only be entered through setting high the RESET<1:0>
bits in the Configuration register. This mode is defined
as the condition where the converters are active, but
their output is forced to ‘0’.
The registers are not affected in this Reset mode and
retain their state, except the data registers of the
corresponding channel, which are reset to ‘0’.
The ADCs can immediately output meaningful codes
after leaving the Reset mode (and after the sinc filter
settling time). This mode is both entered and exited
through setting of bits in the Configuration register.
Each converter can be placed in Soft Reset mode
independently. The configuration registers are not
modified by the Soft Reset mode.
A data ready pulse is not generated by any ADC while
in Reset mode.
Reset mode also affects the modulator output block,
i.e., the MDAT pin, corresponding to the channel in
Reset. If enabled, it provides a bit stream
corresponding to a zero output (a series of 0011 bits
continuously repeated).
When an ADC exits the ADC Reset mode, any phase
delay present before reset was entered is still present.
If one ADC is not in Reset mode, the ADC leaving the
Reset mode automatically resynchronizes the phase
delay relative to the other ADC channel per the phase
delay register block and gives data ready pulses
accordingly.
If an ADC is placed in Reset mode while the other is
converting, it is not shutting down the internal clock.
When going back out of Reset, it is automatically
resynchronized with the clock that did not stop during
Reset.
If both ADCs are in Soft Reset, the clock is no longer
distributed to the digital core for low-power operation.
Once any of the ADC is back to normal operation, the
clock is automatically distributed again.
However, when the two channels are in Soft Reset, the
input structure is still clocking if MCLK is applied to
properly bias the inputs so that no leakage current is
observed. If MCLK is not applied, large analog input
leakage currents can be observed for highly negative
input voltages (typically below -0.6V referred to A
GND
).
4.20 Hard Reset Mode (RESET = D
GND
)
This mode is only available during a POR or when the
RESET
pin is pulled low. The RESET pin low state
places the device in a Hard Reset mode.
In this mode, all internal registers are reset to their
default state.
The DC biases for the analog blocks are still active, i.e.
the MCP3911 is ready to convert. However, this pin
clears all conversion data in the ADCs. In this mode,
the MDAT outputs are in high-impedance. The
comparator’s outputs of both ADCs are forced to their
reset state (0011). The SINC filters are all reset as well
as their double output buffers. See serial timing for
minimum pulse low time in Section 1.0 “Electrical
Characteristics”.
During a Hard Reset, no communication with the part is
possible. The digital interface is maintained in a reset
state.
In this state, to properly bias the input structures of both
channels, the MCLK can be applied to the part. If not
applied, large analog input leakage currents can be
observed for highly negative input signals, and after
removing the RESET state, a certain start-up time is
necessary to bias the input structure properly. During
this delay, the ADC conversions can be inaccurate.
4.21 ADC Shutdown Mode
ADC Shutdown mode is defined as a state where the
converters and their biases are off, consuming only
leakage current. When the Shutdown bit is reset to ‘0’,
the analog biases are enabled as well as the clock and
the digital circuitry. The ADC gives a data ready pulse
after the SINC filter settling time has occurred.
However, since the analog biases are not completely
settled at the beginning of the conversion, the sampling
may not be accurate during about 1 ms (corresponding
to the settling time of the biasing in worst case
conditions). To ensure the accuracy, the data ready
pulse coming within the delay of 1 ms + settling time of
the SINC filter should be discarded.
Each converter can be placed in Shutdown mode
independently. The CONFIG registers are not modified
by the Shutdown mode. This mode is only available
through programming of the SHUTDOWN<1:0> bits
the CONFIG register.
The output data is flushed to all zeros while in ADC
Shutdown mode. No data ready pulses are generated
by any ADC while in ADC Shutdown mode.
ADC Shutdown mode also affects the modulator output
block, i.e. if MDAT of the channel in Shutdown mode is
enabled, this pin provides a bit stream corresponding to
a zero output (series of 0011 bits continuously
repeated).