Datasheet

MCP3911
DS20002286B-page 24  2012-2013 Microchip Technology Inc.
Since this is the output data rate and the decimation
filter is a SINC (or notch) filter, there is a notch in the
filter transfer function at each integer multiple of this
rate.
The following table describes the various combinations
of OSR and PRESCALE and their associated AMCLK,
DMCLK and DRCLK rates.
TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR, AND PRESCALE, MCLK = 4 MHz
PRE
<1:0>
OSR <2:0> OSR AMCLK DMCLK DRCLK
DRCLK
(ksps)
SINAD
(dB)
Note 1
ENOB
from
SINAD
(bits)
Note 1
1 1 1 1 1 4096 MCLK/8 MCLK/32 MCLK/131072 0.035 98 16
1 1 1 1 1 2048 MCLK/8 MCLK/32 MCLK/65536 0.061 98 16
1 1 1 1 1 1024 MCLK/8 MCLK/32 MCLK/32768 0.122 97 15.8
1 1 1 1 1 512 MCLK/8 MCLK/32 MCLK/16384 0.244 96 15.6
1 1 0 1 1 256 MCLK/8 MCLK/32 MCLK/8192 0.488 95 15.5
1 1 0 1 0 128 MCLK/8 MCLK/32 MCLK/4096 0.976 90 14.7
1 1 0 0 1 64 MCLK/8 MCLK/32 MCLK/2048 1.95 83 13.5
1 1 0 0 0 32 MCLK/8 MCLK/32 MCLK/1024 3.9 70 11.3
1 0 1 1 1 4096 MCLK/4 MCLK/16 MCLK/65536 0.061 98 16
1 0 1 1 1 2048 MCLK/4 MCLK/16 MCLK/32768 0.122 98 16
1 0 1 1 1 1024 MCLK/4 MCLK/16 MCLK/16384 0.244 97 15.8
1 0 1 1 1 512 MCLK/4 MCLK/16 MCLK/8192 0.488 96 15.6
1 0 0 1 1 256 MCLK/4 MCLK/16 MCLK/4096 0.976 95 15.5
1 0 0 1 0 128 MCLK/4 MCLK/16 MCLK/2048 1.95 90 14.7
1 0 0 0 1 64 MCLK/4 MCLK/16 MCLK/1024 3.9 83 13.5
1 0 0 0 0 32 MCLK/4 MCLK/16 MCLK/512 7.8125 70 11.3
0 1 1 1 1 4096 MCLK/2 MCLK/8 MCLK/32768 0.122 98 16
0 1 1 1 1 2048 MCLK/2 MCLK/8 MCLK/16384 0.244 98 16
0 1 1 1 1 1024 MCLK/2 MCLK/8 MCLK/8192 0.488 97 15.8
0 1 1 1 1 512 MCLK/2 MCLK/8 MCLK/4096 0.976 96 15.6
0 1 0 1 1 256 MCLK/2 MCLK/8 MCLK/2048 1.95 95 15.5
0 1 0 1 0 128 MCLK/2 MCLK/8 MCLK/1024 3.9 90 14.7
0 1 0 0 1 64 MCLK/2 MCLK/8 MCLK/512 7.8125 83 13.5
0 1 0 0 0 32 MCLK/2 MCLK/8 MCLK/256 15.625 70 11.3
0 0 1 1 1 4096 MCLK MCLK/4 MCLK/16384 0.244 98 16
0 0 1 1 0 2048 MCLK MCLK/4 MCLK/8192 0.488 98 16
0 0 1 0 1 1024 MCLK MCLK/4 MCLK/4096 0.976 97 15.8
0 0 1 0 0 512 MCLK MCLK/4 MCLK/2048 1.95 96 15.6
0 0 0 1 1 256 MCLK MCLK/4 MCLK/1024 3.9 95 15.5
0 0 0 1 0 128 MCLK MCLK/4 MCLK/512 7.8125 90 14.7
0 0 0 0 1 64 MCLK MCLK/4 MCLK/256 15.625 83 13.5
0 0 0 0 0 32 MCLK MCLK/4 MCLK/128 31.25 70 11.3
Note 1: For OSR = 32 and 64, DITHER = None. For OSR = 128 and higher, DITHER = Maximum. The SINAD
values are given from GAIN = 1.