Datasheet

 2012-2013 Microchip Technology Inc. DS20002286B-page 23
MCP3911
4.0 TERMINOLOGIES AND
FORMULAS
This section defines the terms and formulas used
throughout this data sheet. The following terms are
defined:
• MCLK – Master Clock
• AMCLK – Analog Master Clock
• DMCLK - Digital Master Clock
• DRCLK - Data Rate Clock
• OSR – Oversampling Ratio
• Offset Error
• Gain Error
• Integral Non-Linearity Error
• Signal-to-Noise Ratio (SNR)
• Signal-to-Noise Ratio and Distortion (SINAD)
• Total Harmonic Distortion (THD)
• Spurious-Free Dynamic Range (SFDR)
• MCP3911 Delta-Sigma Architecture
• Idle Tones
• Dithering
• Crosstalk
• PSRR
• CMRR
• ADC Reset Mode
• Hard Reset Mode (RESET = DGND)
• ADC Shutdown Mode
• Full Shutdown Mode
4.1 MCLK – Master Clock
This is the fastest clock present in the device. This is
the frequency of the crystal placed at the OSC1/OSC2
inputs when CLKEXT = 0 or the frequency of the clock
input at the OSC1/CLKI when CLKEXT = 1. See
Figure 4-1.
4.2 AMCLK – Analog Master Clock
This is the clock frequency that is present on the analog
portion of the device, after prescaling has occurred via
the CONFIG PRE<1:0> register bits. The analog
portion includes the PGAs and the two Delta-Sigma
modulators.
FIGURE 4-1: Clock Sub-circuitry.
4.3 DMCLK - Digital Master Clock
This is the clock frequency that is present on the digital
portion of the device after prescaling and division by 4.
This is also the sampling frequency, that is the rate at
which the modulator outputs are refreshed. Each
period of this clock corresponds to one sample and one
modulator output. See Figure 4-1.
EQUATION 4-1:
4.4 DRCLK - Data Rate Clock
This is the output data rate, i.e., the rate at which the
ADCs output new data. Each new data is signaled by a
data ready pulse on the DR
pin.
This data rate is depending on the OSR and the
prescaler with the following formula:
EQUATION 4-2:
TABLE 4-1: MCP3911 OVERSAMPLING
RATIO SETTINGS
Config
Analog Master Clock
Prescale
PRE<1:0>
0 0 AMCLK = MCLK/ 1 (default)
0 1 AMCLK = MCLK/ 2
1 0 AMCLK = MCLK/ 4
1 1 AMCLK = MCLK/ 8
AMCLK
MCLK
PRESCALE
-------------------------------
=
DMCLK
AMCLK
4
---------------------
MCLK
4 PRESCALE
×
----------------------------------------==
DRCLK
DMCLK
OSR
----------------------
AMCLK
4OSR
×
---------------------
MCLK
4 OSR PRESCALE
××
-----------------------------------------------------------===